Abstract: In an example, a serial peripheral interface (SPI) flash memory controller includes a transmit first-in-first-out (FIFO) circuit and an SPI interface operable to provide an interface between the transmit FIFO and an SPI flash memory. The SPI flash memory controller further includes a random access memory (RAM) operable to store a memory interface file, an address interface of the RAM operable to receive a command from the transmit FIFO circuit, a data interface of the RAM operable to output a control word associated with the command. The SPI flash memory controller further includes state machine logic operable to set behavior of the SPI interface based on the control word output from the RAM, where the control word includes a data direction field, a data phase field, an addressing width field, an addressing phase field, and a command error field.

Abstract: A circuit for enabling the transfer of data by an integrated circuit device is described. The circuit comprises a non-volatile memory array coupled to receive a clock signal and having a plurality of memory elements storing data; and a control circuit coupled to the non-volatile memory array, the control circuit enabling uni-directional transfer of data on a plurality of signal lines between the non-volatile memory array and the control circuit in a first mode and bi-directional transfer of data in a second mode; wherein the control circuit controls the transfer of data on the plurality of signal lines between the non-volatile memory array and the control circuit in the first mode on both the rising and falling edges of the clock signal. A method of enabling the transfer of data by an integrated circuit device is also described.

Abstract: A circuit for enabling the transfer of data by an integrated circuit device is described. The circuit comprises a non-volatile memory array coupled to receive a clock signal and having a plurality of memory elements storing data; and a control circuit coupled to the non-volatile memory array, the control circuit enabling uni-directional transfer of data on a plurality of signal lines between the non-volatile memory array and the control circuit in a first mode and bi-directional transfer of data in a second mode; wherein the control circuit controls the transfer of data on the plurality of signal lines between the non-volatile memory array and the control circuit in the first mode on both the rising and falling edges of the clock signal. A method of enabling the transfer of data by an integrated circuit device is also described.