Abstract: A method for fabricating a three-dimensional (3D) static random-access memory (SRAM) architecture using catalyst influenced chemical etching (CICE). Utilizing CICE, semiconductor fins can be etched with no etch taper, smooth sidewalls and no maximum height limitation. CICE enables stacking of as many nanosheet layers a desired and also enables a 3D stacked architecture for SRAM cells. Furthermore, CICE can be used to etch silicon waveguides thereby creating waveguides with smooth sidewalls to improve transmission efficiency and, for photon-based quantum circuits, to eliminate charge fluctuations that may affect photon indistinguishability.

Abstract: Trays and methods for medical products packaging, storage and access are described where a multi-level packaging assembly may comprise a top tray level, a lower tray level upon which the top tray level is removably positioned, one or more compartment barriers which define a first compartment within the lower tray level such that the first compartment is sized to accommodate a single syringe. The first compartment barriers may have a continuous ledge at a constant level with respect to a bottom of the lower tray level, and a base which is uninclined relative to the bottom of the lower tray level, and at least one layer of wrap sized so as to fold over and enclose both the lower tray level and the top tray level such that unfolding of the at least one layer of wrap reveals the top tray level.

Abstract: A method for fabricating a three-dimensional (3D) static random-access memory (SRAM) architecture using catalyst influenced chemical etching (CICE). Utilizing CICE, semiconductor fins can be etched with no etch taper, smooth sidewalls and no maximum height limitation. CICE enables stacking of as many nanosheet layers a desired and also enables a 3D stacked architecture for SRAM cells. Furthermore, CICE can be used to etch silicon waveguides thereby creating waveguides with smooth sidewalls to improve transmission efficiency and, for photon-based quantum circuits, to eliminate charge fluctuations that may affect photon indistinguishability.

Abstract: A method for fabricating a three-dimensional (3D) static random-access memory (SRAM) architecture using catalyst influenced chemical etching (CICE). Utilizing CICE, semiconductor fins can be etched with no etch taper, smooth sidewalls and no maximum height limitation. CICE enables stacking of as many nanosheet layers a desired and also enables a 3D stacked architecture for SRAM cells. Furthermore, CICE can be used to etch silicon waveguides thereby creating waveguides with smooth sidewalls to improve transmission efficiency and, for photon-based quantum circuits, to eliminate charge fluctuations that may affect photon indistinguishability.

Abstract: A method for fabricating a three-dimensional (3D) static random-access memory (SRAM) architecture using catalyst influenced chemical etching (CICE). Utilizing CICE, semiconductor fins can be etched with no etch taper, smooth sidewalls and no maximum height limitation. CICE enables stacking of as many nanosheet layers a desired and also enables a 3D stacked architecture for SRAM cells. Furthermore, CICE can be used to etch silicon waveguides thereby creating waveguides with smooth sidewalls to improve transmission efficiency and, for photon-based quantum circuits, to eliminate charge fluctuations that may affect photon indistinguishability.

Abstract: A method for fabricating a flash memory device where the flash memory device includes a substantially uniform size and spatial distribution of nanoparticles on a tunnel oxide layer to form a floating gate. The flash memory device may be fabricated by defining active areas in a substrate and forming an oxide layer on the substrate. A self-assembled protein lattice may be formed on top of the oxide layer where the self-assembled protein lattice includes a plurality of molecular chaperones. The cavities of the chaperones may provide confined spaces where nanocrystals can be trapped thereby forming an ordered nanocrystal lattice. A substantially uniform distribution of nanocrystals may be formed on the oxide layer upon removal of the self-assembled protein lattice such as through high temperature annealing.

Abstract: Systems and methods are disclosed to automatically generate a processor architecture for a custom integrated circuit (IC) described by a computer readable code. The IC has one or more timing and hardware constraints. The system extracts parameters defining the processor architecture from a static profile and a dynamic profile of the computer readable code; iteratively optimizes the processor architecture by changing one or more parameters until all timing and hardware constraints expressed as a cost function are met; and synthesizes the generated processor architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.

Abstract: A process for creating a beryllium oxide film on the surface of a semiconductor material is disclosed. The process is useful for making gate dielectric layers for metal-oxide-semiconductor (MOS) devices, particularly III-V semiconductor devices.

Abstract: Systems and methods are disclosed to automatically generate a processor architecture for a custom integrated circuit (IC) described by a computer readable code. The IC has one or more timing and hardware constraints. The system extracts parameters defining the processor architecture from a static profile and a dynamic profile of the computer readable code; iteratively optimizes the processor architecture by changing one or more parameters until all timing and hardware constraints expressed as a cost function are met; and synthesizes the generated processor architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.

Abstract: Systems and methods are disclosed to automatically generate software development tools for an automatically generated processor architecture by: receiving a description of a target processor; automatically generating a target compiler using a compiler generator; automatically generating a target assembler using an assembler generator; automatically generating a target linker using a linker generator; automatically generating a target simulator using a simulator generator; automatically generating a target profiler using a profiler generator; iteratively generating a new processor architecture by changing one or more parameters of the processor architecture until all user constraints or requirements are met using the generated target compiler, assembler, linker, simulator, and profiler; for each new processor architecture regenerating the target compiler, assembler, linker, simulator, profiler for the new processor architecture; and synthesizing an optimal generated processor architecture into a computer reada

Abstract: A method and semiconductor device for forming a uniformly thin dielectric layer on graphene. A metal or semiconductor layer is deposited on graphene which is located on the surface of a dielectric layer or on the surface of a substrate. The metal or semiconductor layer may act as a nucleation layer for graphene. The metal or semiconductor layer may be subjected to an oxidation process. A thin dielectric layer may then be formed on the graphene layer after the metal or semiconductor layer is oxidized. As a result of synthesizing a metal-oxide layer on graphene, which acts as a nucleation layer for the gate dielectric and buffer to graphene, a uniformly thin dielectric layer may be established on graphene without affecting the underlying characteristics of graphene.

Abstract: Systems and methods are disclosed to automatically generate a processor architecture for a custom integrated circuit (IC) described by a computer readable code. The IC has one or more timing and hardware constraints. The system extracts parameters defining the processor architecture from a static profile and a dynamic profile of the computer readable code; iteratively optimizes the processor architecture by changing one or more parameters until all timing and hardware constraints expressed as a cost function are met; and synthesizes the generated processor architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.

Abstract: A semiconductor device and method for fabricating a semiconductor device incorporating gate control over a resonant tunneling structure. The semiconductor device includes a source terminal, a gate terminal, a drain terminal, and a resonant tunneling structure located beneath or adjacent to the gate terminal, where the gate terminal controls an electrostatic potential drop through the resonant tunneling structure as well as controlling a potential within a portion of the conduction channel immediately beneath the gate terminal as in a MOSFET. The semiconductor device is fabricated by growing epitaxial layers of tunnel barriers and quantum wells, where a quantum well is formed between each set of two tunneling barriers. Additionally, the epitaxial layers of tunnel barriers and quantum wells are grown, etched and patterned to form a resonant tunneling structure. Further, the semiconductor device is grown, etched and patterned to form a gate, source and drain electrode.

Abstract: A semiconductor device and method for fabricating a semiconductor device incorporating gate control over a resonant tunneling structure. The semiconductor device includes a source terminal, a gate terminal, a drain terminal, and a resonant tunneling structure located beneath or adjacent to the gate terminal, where the gate terminal controls an electrostatic potential drop through the resonant tunneling structure as well as controlling a potential within a portion of the conduction channel immediately beneath the gate terminal as in a MOSFET. The semiconductor device is fabricated by growing epitaxial layers of tunnel barriers and quantum wells, where a quantum well is formed between each set of two tunneling barriers. Additionally, the epitaxial layers of tunnel barriers and quantum wells are grown, etched and patterned to form a resonant tunneling structure. Further, the semiconductor device is grown, etched and patterned to form a gate, source and drain electrode.

Abstract: A method and semiconductor device for forming a uniformly thin dielectric layer on graphene. A metal or semiconductor layer is deposited on graphene which is located on the surface of a dielectric layer or on the surface of a substrate. The metal or semiconductor layer may act as a nucleation layer for graphene. The metal or semiconductor layer may be subjected to an oxidation process. A thin dielectric layer may then be formed on the graphene layer after the metal or semiconductor layer is oxidized. As a result of synthesizing a metal-oxide layer on graphene, which acts as a nucleation layer for the gate dielectric and buffer to graphene, a uniformly thin dielectric layer may be established on graphene without affecting the underlying characteristics of graphene.

Abstract: A method and semiconductor device for integrating the fabrication of a photodetector with the fabrication of a CMOS device on a SOI substrate. The SOI substrate is divided into two regions, a CMOS region and an optical detecting region. After the CMOS device is fabricated in the CMOS region, the optical detecting region is patterned and etched through the top silicon layer and the buried oxide layer to the base silicon layer. The pattern is etched to a depth so that after a material of a photodetector is deposited in the etched pattern, the material grows to the surface level of the SOI substrate. After the formation of a photodetector structure in the optical detecting region, the metallization process is performed on the CMOS device and the photodetector. In this manner, the fabrication of a photodetector is integrated with the fabrication of a CMOS device on the SOI substrate.

Abstract: A method for fabricating a flash memory device where the flash memory device includes a substantially uniform size and spatial distribution of nanoparticles on a tunnel oxide layer to form a floating gate. The flash memory device may be fabricated by defining active areas in a substrate and forming an oxide layer on the substrate. A self-assembled protein lattice may be formed on top of the oxide layer where the self-assembled protein lattice includes a plurality of molecular chaperones. The cavities of the chaperones may provide confined spaces where nanocrystals can be trapped thereby forming an ordered nanocrystal lattice. A substantially uniform distribution of nanocrystals may be formed on the oxide layer upon removal of the self-assembled protein lattice such as through high temperature annealing.

Abstract: Techniques and a set of heuristics are described to perform allocation of the special instruction memory where indirect very long instruction words (VLIW's) are stored for the ManArray family of multiprocessor digital signal processors (DSP). This approach substantially reduces the cost of pre-initializing the contents of VLIWs.

Abstract: A thin film transistor includes: a) a thin film transistor layer comprising a source region, a channel region and a drain region; the thin film transistor layer further comprising a drain offset region positioned between the drain region and the channel region; b) the channel region being substantially polycrystalline and having a first average crystalline grain size; and c) the drain offset region being substantially polycrystalline and having a second average crystalline grain size, the second average crystalline grain size being larger than the first average crystalline grain size. A method for forming such a construction using polycrystalline materials, preferably polysilicon, and an amorphizing silicon implant with subsequent recrystallization is also disclosed.

Abstract: Techniques and a set of heuristics are described to perform allocation of the special instruction memory where indirect very long instruction words (VLIW's) are stored for the ManArray family of multiprocessor digital signal processors (DSP). This approach substantially reduces the cost of pre-initializing the contents of VLIWs.