Patents by Inventor Sanjay Bhagawan Patil
Sanjay Bhagawan Patil has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10152101Abstract: Systems and methods relate to controlling voltage deviations in processing systems. A scheduler receives transactions and to be issued for execution in a pipeline. A voltage deviation that will occur if a particular transaction is executed in the pipeline is estimated before the transaction is issued. Threshold comparators are used to determine if the estimated voltage deviation will exceed specified thresholds to cause voltage overshoots or undershoots. The scheduler is configured to implement one or more corrective measures, such as increasing or decreasing energy in the pipeline, to mitigate possible voltage overshoots or undershoots, before the transaction is issued to be executed in the pipeline.Type: GrantFiled: September 22, 2015Date of Patent: December 11, 2018Assignee: QUALCOMM IncorporatedInventors: Eric Wayne Mahurin, Sanjay Bhagawan Patil, Martin Pierre Saint-Laurent
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Patent number: 10133285Abstract: A computer-readable storage medium for controlling voltage droop storing instructions that, when executed by a processor, cause a device to perform operations including receiving a first voltage to a first input of a first component of a device. The first voltage corresponding to a first logical value causes a first internal power supply of the first component to be charged using an external power supply. The operations further include providing a second voltage to a second input of a second component of the device in response to a first voltage level of the first internal power supply satisfying a second voltage level. The second voltage corresponding to the first logical value causes a second internal power supply of the second component of the device to be charged using the external power supply.Type: GrantFiled: October 23, 2017Date of Patent: November 20, 2018Assignee: QUALCOMM IncorporatedInventors: Sanjay Bhagawan Patil, Daniel Stasiak, Martin Pierre Saint-Laurent, Rui Li, Bin Liang, Sei Seung Yoon, Chulmin Jung
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Publication number: 20180046209Abstract: A computer-readable storage medium for controlling voltage droop storing instructions that, when executed by a processor, cause a device to perform operations including receiving a first voltage to a first input of a first component of a device. The first voltage corresponding to a first logical value causes a first internal power supply of the first component to be charged using an external power supply. The operations further include providing a second voltage to a second input of a second component of the device in response to a first voltage level of the first internal power supply satisfying a second voltage level. The second voltage corresponding to the first logical value causes a second internal power supply of the second component of the device to be charged using the external power supply.Type: ApplicationFiled: October 23, 2017Publication date: February 15, 2018Inventors: Sanjay Bhagawan Patil, Daniel Stasiak, Martin Pierre Saint-Laurent, Rui Li, Bin Liang, Sei Seung Yoon, Chulmin Jung
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Patent number: 9851730Abstract: Voltage droop control is disclosed. A device includes a first component coupled to an external power supply and a second component coupled to the external power supply. The first component includes a first input configured to receive a first voltage, a first internal power supply configured to be charged by the external power supply in response to the first voltage corresponding to a first logical value, and a voltage droop controller configured to output a second voltage via a first output. The second voltage corresponds to the first logical value in response to a first voltage level of the first internal power supply satisfying a second voltage level. The second component includes a second input configured to receive the second voltage from the first output.Type: GrantFiled: April 10, 2015Date of Patent: December 26, 2017Assignee: QUALCOMM IncorporatedInventors: Sanjay Bhagawan Patil, Daniel Stasiak, Martin Pierre Saint-Laurent, Rui Li, Bin Liang, Sei Seung Yoon, Chulmin Jung
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Patent number: 9804650Abstract: An apparatus includes a first node configured to provide a first supply voltage to a first device and a second node configured to provide a second supply voltage to a second device. The apparatus further includes a bus configured to communicatively couple the first device and the second device. The apparatus also includes a switch configured to couple the first node and the second node.Type: GrantFiled: January 22, 2015Date of Patent: October 31, 2017Assignee: QUALCOMM IncorporatedInventors: Sanjay Bhagawan Patil, Daniel Stasiak, Martin Pierre Saint-Laurent
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Publication number: 20170083066Abstract: Systems and methods relate to controlling voltage deviations in processing systems. A scheduler receives transactions and to be issued for execution in a pipeline. A voltage deviation that will occur if a particular transaction is executed in the pipeline is estimated before the transaction is issued. Threshold comparators are used to determine if the estimated voltage deviation will exceed specified thresholds to cause voltage overshoots or undershoots. The scheduler is configured to implement one or more corrective measures, such as increasing or decreasing energy in the pipeline, to mitigate possible voltage overshoots or undershoots, before the transaction is issued to be executed in the pipeline.Type: ApplicationFiled: September 22, 2015Publication date: March 23, 2017Inventors: Eric Wayne MAHURIN, Sanjay Bhagawan PATIL, Martin Pierre SAINT-LAURENT
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Patent number: 9552033Abstract: Latency-based power mode units for controlling power modes of processor cores, and related methods and systems are disclosed. In one aspect, the power mode units are configured to reduce power provided to the processor core when the processor core has one or more threads in pending status and no threads in active status. An operand of an instruction being processed by a thread may be data in memory located outside processor core. If the processor core does not require as much power to operate while a thread waits for a request from outside the processor core, the power consumed by the processor core can be reduced during these waiting periods. Power can be conserved in the processor core even when threads are being processed if the only threads being processed are in pending status, and can reduce the overall power consumption in the processor core and its corresponding CPU.Type: GrantFiled: April 22, 2014Date of Patent: January 24, 2017Assignee: QUALCOMM IncorporatedInventors: Suresh Kumar Venkumahanti, Peter Gene Sassone, Sanjay Bhagawan Patil
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Publication number: 20160299517Abstract: Voltage droop control is disclosed. A device includes a first component coupled to an external power supply and a second component coupled to the external power supply. The first component includes a first input configured to receive a first voltage, a first internal power supply configured to be charged by the external power supply in response to the first voltage corresponding to a first logical value, and a voltage droop controller configured to output a second voltage via a first output. The second voltage corresponds to the first logical value in response to a first voltage level of the first internal power supply satisfying a second voltage level. The second component includes a second input configured to receive the second voltage from the first output.Type: ApplicationFiled: April 10, 2015Publication date: October 13, 2016Inventors: Sanjay Bhagawan Patil, Daniel Stasiak, Martin Pierre Saint-Laurent, Rui Li, Bin Liang, Sei Seung Yoon, Chulmin Jung
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Publication number: 20160070323Abstract: An apparatus includes a first node configured to provide a first supply voltage to a first device and a second node configured to provide a second supply voltage to a second device. The apparatus further includes a bus configured to communicatively couple the first device and the second device. The apparatus also includes a switch configured to couple the first node and the second node.Type: ApplicationFiled: January 22, 2015Publication date: March 10, 2016Inventors: Sanjay Bhagawan Patil, Daniel Stasiak, Martin Pierre Saint-Laurent
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Publication number: 20150301573Abstract: Latency-based power mode units for controlling power modes of processor cores, and related methods and systems are disclosed. In one aspect, the power mode units are configured to reduce power provided to the processor core when the processor core has one or more threads in pending status and no threads in active status. An operand of an instruction being processed by a thread may be data in memory located outside processor core. If the processor core does not require as much power to operate while a thread waits for a request from outside the processor core, the power consumed by the processor core can be reduced during these waiting periods. Power can be conserved in the processor core even when threads are being processed if the only threads being processed are in pending status, and can reduce the overall power consumption in the processor core and its corresponding CPU.Type: ApplicationFiled: April 22, 2014Publication date: October 22, 2015Applicant: QUALCOMM IncorporatedInventors: Suresh Kumar Venkumahanti, Peter Gene Sassone, Sanjay Bhagawan Patil