Abstract: Semiconductor devices having air gap spacers that are formed as part of BEOL or MOL layers of the semiconductor devices are provided, as well as methods for fabricating such air gap spacers. For example, a method comprises forming a first metallic structure and a second metallic structure on a substrate, wherein the first and second metallic structures are disposed adjacent to each other with insulating material disposed between the first and second metallic structures. The insulating material is etched to form a space between the first and second metallic structures. A layer of dielectric material is deposited over the first and second metallic structures using a pinch-off deposition process to form an air gap in the space between the first and second metallic structures, wherein a portion of the air gap extends above an upper surface of at least one of the first metallic structure and the second metallic structure.

Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor device comprising: a bottom field effect transistor (FET); a top FET stacked over the bottom FET, where the top FET has a smaller active area than the bottom FET; a bottom gate formed in contact with the bottom FET; a top gate formed in contact with the top FET; and a bottom contact formed adjacent to the top gate, wherein an inner spacer is formed between the bottom contact and the top gate.

Abstract: A high density memory apparatus includes a plurality of transistors vertically stacked on top of each other. The plurality of transistors share a common source structure, but each of the plurality of transistors has its own horizontal nanosheet and gate stack that are separate from respective horizontal channel structures and gate stacks of the others of the plurality of transistors. Ends of the nanosheets distal from the gate stacks are doped to act as drains for the transistors. Each of a plurality of two-terminal memory units is electrically connected to the drain end of a corresponding one of the nanosheets. Some embodiments achieve in excess of 5000 memory bits/square micrometer (?m2); in some embodiments, in excess of 6000 bits/?m2.

Abstract: A first and a second nanosheet stack, a shallow trench isolation region vertically aligned between them, a continuous dielectric layer below the first and second nanosheet stack and above the shallow trench isolation region. The shallow trench isolation region is vertically aligned with a source drain between the first and the second nanosheet stack. A method including forming a first and a second nanosheet stack on a first substrate, the first and the second nanosheet stack each including a lower nanosheet stack vertically aligned above an upper nanosheet stack, the upper nanosheet stack and the lower nanosheet stack each including alternating layers of a sacrificial material and a semiconductor channel material vertically aligned and stacked one on top of another, flipping the first substrate over, bonding an upper surface of the first substrate to an upper surface of a second substrate which includes a shallow trench isolation region.

Abstract: A lower nanosheet stack including alternating layers of a first work function metal and a semiconductor channel material, an upper nanosheet stack including alternating layers of a second work function metal and the semiconductor channel material, one or more dielectric layers between the lower nanosheet stack and the upper nanosheet stack, each separated by an inner spacer. An embodiment where the one or more partial dielectric layers each include an opening. Forming an upper nanosheet stack vertically aligned above an intermediate stack, vertically aligned above a lower nanosheet stack, the upper nanosheet stack, the lower nanosheet stack each including alternating layers of a first sacrificial material and a semiconductor channel material, the intermediate stack including one or more alternating layers of the sacrificial material and a second sacrificial material, recessing the second sacrificial material; and forming second inner spacers where the second sacrificial material was recessed.

Abstract: A phase change memory structure including a bottom electrode; a top electrode; a first phase change material between the bottom electrode and the top electrode; a first dielectric surrounding the first phase change material; a second dielectric surrounding the top electrode, the second dielectric having selective adhesion to a metal as compared to the first phase change material; a first metal feature contacting the bottom electrode; and a second metal feature contacting the top electrode.

Abstract: Semiconductor devices having air gap spacers that are formed as part of BEOL or MOL layers of the semiconductor devices are provided, as well as methods for fabricating such air gap spacers. For example, a method comprises forming a first metallic structure and a second metallic structure on a substrate, wherein the first and second metallic structures are disposed adjacent to each other with insulating material disposed between the first and second metallic structures. The insulating material is etched to form a space between the first and second metallic structures. A layer of dielectric material is deposited over the first and second metallic structures using a pinch-off deposition process to form an air gap in the space between the first and second metallic structures, wherein a portion of the air gap extends above an upper surface of at least one of the first metallic structure and the second metallic structure.

Abstract: A semiconductor structure includes a heater located in a first layer of a device, wherein the heater is surrounded by a dielectric, a phase change memory (PCM) liner in direct contact with a top surface of the heater in a second layer of the device, a spacer disposed adjacent the PCM liner in the second layer of the device, and a PCM stack disposed above the PCM liner in the second layer of the device.

Abstract: A semiconductor structure may include a heater surrounded by a dielectric layer, a projection liner on top of the heater, a phase change material layer above the projection liner, and a top electrode contact surrounding a top portion of the phase change material layer, The projection liner may cover a top surface of the heater. The projection liner may separate the phase change material layer from the second dielectric layer and the heater. The projection liner may provide a parallel conduction path in the crystalline phase and the amorphous phase of the phase change material layer. The top electrode contact may be separated from the phase change material layer by a metal liner. The semiconductor structure may include a bottom electrode below and in electrical contact with the heater and a top electrode above and in electrical contact with the phase change material layer.

Abstract: A semiconductor structure may include a heater surrounded by a dielectric layer, a projection liner on top of the heater, a phase change material layer above the projection liner, and a top electrode contact surrounding a top portion of the phase change material layer, The projection liner may cover a top surface of the heater. The projection liner may separate the phase change material layer from the second dielectric layer and the heater. The projection liner may provide a parallel conduction path in the crystalline phase and the amorphous phase of the phase change material layer. The top electrode contact may be separated from the phase change material layer by a metal liner. The semiconductor structure may include a bottom electrode below and in electrical contact with the heater and a top electrode above and in electrical contact with the phase change material layer.

Abstract: A vertical transport fin field effect transistor (VT FinFET), including one or more vertical fins on a surface of a substrate, an L-shaped or U-shaped spacer trough on the substrate adjacent to at least one of the one or more vertical fins, and a gate dielectric layer on the sidewalls of the at least one of the one or more vertical fins and the L-shaped or U-shaped spacer trough.

Abstract: A phase change material memory device is provided. The phase change material memory device includes one or more electrical contacts in a substrate, and a dielectric cover layer on the electrical contacts and substrate. The phase change material memory device further includes a lower conductive shell in a trench above one of the one or more electrical contacts, and an upper conductive shell on the lower conductive shell in the trench. The phase change material memory device further includes a conductive plug filling the upper conductive shell. The phase change material memory device further includes a liner layer on the dielectric cover layer and conductive plug, and a phase change material block on the liner layer on the dielectric cover layer and in the trench.

Abstract: A method of forming a punch through stop region in a fin structure is disclosed. The method may include forming a doped glass layer on a fin structure and forming a masking layer on the doped glass layer. The method may further include removing a portion of the masking layer from an active portion of the fin structure, and removing an exposed portion the doped glass layer that is present on the active portion of the fin structure. A remaining portion of the doped glass layer is present on the isolation portion of the fin structure. Dopant from the doped glass layer may then be diffused into the isolation portion of the fin structure to form the punch through stop region between the active portion of the fin structure and a supporting substrate.

Abstract: A method of forming a punch through stop region in a fin structure is disclosed. The method may include forming a doped glass layer on a fin structure and forming a masking layer on the doped glass layer. The method may further include removing a portion of the masking layer from an active portion of the fin structure, and removing an exposed portion the doped glass layer that is present on the active portion of the fin structure. A remaining portion of the doped glass layer is present on the isolation portion of the fin structure. Dopant from the doped glass layer may then be diffused into the isolation portion of the fin structure to form the punch through stop region between the active portion of the fin structure and a supporting substrate.

Abstract: A phase change material memory device is provided. The phase change material memory device includes one or more electrical contacts in a substrate, and a dielectric cover layer on the electrical contacts and substrate. The phase change material memory device further includes a lower conductive shell in a trench above one of the one or more electrical contacts, and an upper conductive shell on the lower conductive shell in the trench. The phase change material memory device further includes a conductive plug filling the upper conductive shell. The phase change material memory device further includes a liner layer on the dielectric cover layer and conductive plug, and a phase change material block on the liner layer on the dielectric cover layer and in the trench.

Abstract: A technique relates to a semiconductor device. A gate stack is formed on a fin, the gate stack being formed to have a length in a vertical direction. A gate contact is formed adjacent to the gate stack for the length of the gate stack in the vertical direction.

Abstract: A gate tie-down structure includes a gate structure including a gate conductor and gate spacers and inner spacers formed on the gate spacers. Trench contacts are formed on sides of the gate structure. An interlevel dielectric (ILD) has a thickness formed over the gate structure. A horizontal connection is formed within the thickness of the ILD over an active area connecting the gate conductor and one of the trench contacts over one of the inner spacers.

Abstract: A vertical transport fin field effect transistor (VT FinFET), including one or more vertical fins on a surface of a substrate, an L-shaped or U-shaped spacer trough on the substrate adjacent to at least one of the one or more vertical fins, and a gate dielectric layer on the sidewalls of the at least one of the one or more vertical fins and the L-shaped or U-shaped spacer trough.

Abstract: A method of forming a semiconductor device that includes providing a vertically orientated channel region; and converting a portion of an exposed source/drain contact surface of the vertically orientated channel region into an amorphous crystalline structure. The amorphous crystalline structure is from the vertically orientated channel region. An in-situ doped extension region is epitaxially formed on an exposed surface of the vertically orientated channel region. A source/drain region is epitaxially formed on the in-situ doped extension region.

Abstract: A semiconductor structure includes a plurality of semiconductor material fins located on a surface of a substrate. At least one gate structure straddles over a portion of each semiconductor material fin. Unmerged source-side epitaxial semiconductor material portions are located on an exposed surfaces of each semiconductor material fin and on one side of each gate structure and unmerged drain-side epitaxial semiconductor portions are located on other exposed surfaces of each semiconductor material fin and on another side of each gate structure. An etch stop structure is located between each unmerged source-side and drain-side epitaxial semiconductor material portions. Each etch stop structure includes a bottom material portion that has a higher etch resistance in a specific etchant as compared to an upper material portion of the etch stop structure.