Abstract: Integrated circuits such as programmable logic device integrated circuits with memory interface circuitry are provided. The memory interface circuitry measures the timing characteristics of an associated memory during a series of dummy read operations. A multiplexer and phase detector are used to measure phase shifts of memory group clock signals compared to a system clock signal. The memory interface circuitry uses these measurements to adjust a delay-locked-loop circuit. The delay-locked-loop circuit produces a capture clock that is used to read data from the memory.

Abstract: Methods and apparatus provide PCI Express support on a programmable device. A device includes a hard-coded transceiver that supports functionality associated with the PCI Express physical layer and link layer. The hard-coded transceiver can also support part of the PCI Express transaction layer. Soft-coded logic is used to support higher layer functionality including a portion of the transaction layer to allow custom configuration of PCI Express features such as virtual channels, buffers, prioritization, and quality of service characteristics. The hybrid solution reduces logic resource cost and provides an effective custom configurable solution.

Abstract: A programmable device I/O architecture allows for a variable number of I/O banks. Each I/O bank is of an I/O bank type. Each I/O bank type has a fixed number of I/O pins. I/O banks of the same I/O type are compatible within the same programmable device and between different types of programmable devices. The number of I/O pins for each I/O bank type is selected so that each of a set of interfaces can be implemented efficiently using I/O banks of at least one I/O bank type. The largest size I/O bank type and intermediate size I/O bank types are adapted to be a compatible supersets of every smaller I/O bank type. The ratio between data pins and support pins in each I/O bank type is the same. Support pins are regularly distributed between data pins in each I/O bank type.

Abstract: Methods and apparatus are provided for providing PCI Express support. A device includes a hard-coded transceiver configured to support protocols such as Fibre Channel and the 10 Gigabit Attachment Unit Interface (XAUI), but the transceiver does not fully support PCI Express. Interface circuitry is configured to supplement or replace hard-coded transceiver components to provide PCI Express support. Interface circuitry allows PCI Express cores to operate with the transceiver that does not fully support PCI Express.