Abstract: For use in a wireless communication network, an apparatus for sending and receiving an acknowledgment message. The apparatus comprises: 1) a channel controller capable of assigning a common control channel to a mobile station wherein the channel controller is capable of dedicating the common control channel to the mobile station for a predetermined period of time; and 2) a transceiver coupled to the channel controller capable of transmitting and receiving the acknowledgment message on the common control channel.

Abstract: Data which must be memory equalized across a redundant, high availability system utilizing processor-based components is structured in memory segments which form data packets for a data link between active and standby components. Direct memory access is employed to copy memory segments within the active component into a queue for the data link, which transfers memory segments without utilizing the processor within the active component while automatically verifying data integrity and acknowledging successful data transfers. The direct memory access copying of memory segments to the queue may be triggered for changed memory segments by either the processor or specialized hardware within the active component, or may be run in a continuous loop sequencing through a predefined range of memory segments. The standby component may thus be kept abreast of changes to data within memory segments, such as changes to call states or resource allocation records relating to call processing.

Abstract: For use in a wireless communication network, an apparatus for sending and receiving an acknowledgment message. The apparatus comprises: 1) a channel controller capable of assigning a common control channel to a mobile station wherein the channel controller is capable of dedicating the common control channel to the mobile station for a predetermined period of time; and 2) a transceiver coupled to the channel controller capable of transmitting and receiving the acknowledgment message on the common control channel.

Abstract: Data which must be memory equalized across a redundant, high availability system utilizing processor-based components is structured in memory segments which form data packets for a data link between active and standby components. Direct memory access is employed to copy memory segments within the active component into a queue for the data link, which transfers memory segments without utilizing the processor within the active component while automatically verifying data integrity and acknowledging successful data transfers. The direct memory access copying of memory segments to the queue may be triggered for changed memory segments by either the processor or specialized hardware within the active component, or may be run in a continuous loop sequencing through a predefined range of memory segments. The standby component may thus be kept abreast of changes to data within memory segments, such as changes to call states or resource allocation records relating to call processing.