Patents by Inventor Sanjay D. MEHTA

Sanjay D. MEHTA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12176920
    Abstract: Embodiment herein provide a Bose-Chadhuri-Hocquenghem (BCH) encoder for generating a BCH signal. The BCH encoder (1) includes a memory for storing a minimum distance to be used for generating the BCH signal for a BCH code (n, k) and a polynomial generator for generating a generator polynomial for the BCH code (n, k) and encoding the generator polynomial to obtain the BCH signal. The polynomial generator includes a set of k registers (4) connected in series to receive the information bits and output an encoded bit based on a clock signal, a first gate (5) to receive a code length, a number of information bits, and the minimum distance as input, a second gate (6), and a finite field adder circuit (7) for determining a finite field sum of the output of each register of the set of k registers (4).
    Type: Grant
    Filed: September 21, 2021
    Date of Patent: December 24, 2024
    Assignee: INDIAN SPACE RESEARCH ORGANISATION
    Inventors: Deepak Mishra, Neeraj Mishra, Sanjay D. Mehta
  • Publication number: 20240063824
    Abstract: Embodiment herein provide a Bose-Chadhuri-Hocquenghem (BCH) encoder for generating a BCH signal. The BCH encoder (1) includes a memory for storing a minimum distance to be used for generating the BCH signal for a BCH code (n, k) and a polynomial generator for generating a generator polynomial for the BCH code (n, k) and encoding the generator polynomial to obtain the BCH signal. The polynomial generator includes a set of k registers (4) connected in series to receive the information bits and output an encoded bit based on a clock signal, a first gate (5) to receive a code length, a number of information bits, and the minimum distance as input, a second gate (6), and a finite field adder circuit (7) for determining a finite field sum of the output of each register of the set of k registers (4).
    Type: Application
    Filed: September 21, 2021
    Publication date: February 22, 2024
    Applicant: INDIAN SPACE RESEARCH ORGANISATION
    Inventors: Deepak MISHRA, Neeraj MISHRA, Sanjay D. MEHTA