Patents by Inventor Sanjay Dabral

Sanjay Dabral has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • METHOD, SYSTEM, AND APPARATUS FOR LINK LATENCY MANAGEMENT
    Publication number: 20140156892
    Abstract: A link latency management for a high-speed point-to-point network (pTp) is described The link latency management facilitates calculating latency of a serial interface by tracking a round trip delay of a header that contains latency information. Therefore, the link latency management facilitates testers, logic analyzers, or test devices to accurately measure link latency for a point-to-point architecture utilizing a serial interface.
    Type: Application
    Filed: June 10, 2013
    Publication date: June 5, 2014
    Inventors: Tim Frodsham, Michael J. Tripp, David J. O'Brien, Navada Herur Muraleedhara, Naveen Cherukuri, Sanjay Dabral, David S. Dunning, Theodore Z. Schoenborn
  • I/O link with configurable forwarded and derived clocks
    Patent number: 8315347
    Abstract: An electronic communications receiver includes a derived clock signal circuit operable to receive a data signal and to derive a derived clock signal from the received data signal. A separate forwarded clock signal circuit is further operable to receive a forwarded clock signal, and a clock management circuit is operable to receive signals from the derived clock signal circuit and the forwarded clock signal circuit, and to output an output clock signal.
    Type: Grant
    Filed: December 1, 2009
    Date of Patent: November 20, 2012
    Assignee: Intel Corporation
    Inventors: Karthisha S. Canagasaby, Sanjay Dabral
  • Redundant acknowledgment in loopback entry
    Patent number: 8250416
    Abstract: Redundant acknowledgment between agents performing a loopback test over bidirectional communications bus is described. In one example, in a processor including a communications agent coupled to a bidirectional communications bus, the communications agent initiates loopback communications to a second agent, sends a packet including a redundant acknowledgment sequence to the second agent, receives the packet including the redundant acknowledgement sequence looped back from the second agent, determines whether the received redundant acknowledgment sequence is valid, sends a test sequence to the second agent, receives the test sequence looped back, and if the received redundant acknowledgment sequence is determined to be valid, then checks the received test sequence.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: August 21, 2012
    Assignee: Intel Corporation
    Inventors: Tim Frodsham, Zale Schoenborn, Sanjay Dabral, Muraleedhara Navada
  • Technique for lane virtualization
    Patent number: 8204067
    Abstract: A technique to perform virtualization of lanes within a common system interface (CSI) link. More particularly, embodiments described herein relate to virtualizing interconnective paths between two or more electronic devices residing in an electronic network.
    Type: Grant
    Filed: July 13, 2004
    Date of Patent: June 19, 2012
    Assignee: Intel Corporation
    Inventors: Naveen Cherukuri, Jeffrey R. Wilcox, Sanjay Dabral, David S. Dunning, Tim Frodsham, Theodore Z. Schoenborn
  • Apparatuses, systems and methods for detecting errors in data streams on point-to-point serial links
    Patent number: 8195996
    Abstract: Methods, apparatuses and systems for physical link error data capture and analysis. A receiver is coupled to receive a data stream via a point-to-point serial link. A control circuit is coupled with the receiver to cause the receiver to selectively sample the data stream according to an offset parameter and an interval parameter. Comparison circuitry compares the data stream sample to expected data values to determine a bit error rate.
    Type: Grant
    Filed: May 5, 2008
    Date of Patent: June 5, 2012
    Assignee: Intel Corporation
    Inventors: Timothy Frodsham, Zale T. Schoenborn, Sanjay Dabral, Murateendhara Navada
  • Input/output driver swing control and supply noise rejection
    Patent number: 8143911
    Abstract: In general, in one aspect, the disclosure describes an apparatus having an averager to receive differential output voltages of a transmitter and generate an average transmitter output voltage. A comparator is to compare the average transmitter output voltage to a reference voltage and generate a difference therebetween. An integrator is to integrate the difference between the average transmitter output voltage and the reference voltage over time. The integrated difference is fed back to the transmitter to bias the transmitter.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: March 27, 2012
    Assignee: Intel Corporation
    Inventors: Zuoguo Wu, Feng Chen, Sanjay Dabral
  • Dynamically Modulating Link Width
    Publication number: 20120011276
    Abstract: Systems and methods of managing a link provide for receiving a remote width capability during a link initialization, the remote width capability corresponding to a remote port. A link between a local port and the remote port is operated at a plurality of link widths in accordance with the remote width capability.
    Type: Application
    Filed: September 22, 2011
    Publication date: January 12, 2012
    Inventors: Naveen Cherukuri, Aaron T. Spink, Phanindra Mannaya, Tim Frodsham, Jeffrey R. Wilcox, Sanjay Dabral, David Dunning, Theodore Z. Schoenborn
  • Dynamically modulating link width
    Patent number: 8046488
    Abstract: Systems and methods of managing a link provide for receiving a remote width capability during a link initialization, the remote width capability corresponding to a remote port. A link between a local port and the remote port is operated at a plurality of link widths in accordance with the remote width capability.
    Type: Grant
    Filed: May 21, 2004
    Date of Patent: October 25, 2011
    Assignee: Intel Corporation
    Inventors: Naveen Cherukuri, Aaron T. Spink, Phanindra Mannava, Tim Frodsham, Jeffrey R. Wilcox, Sanjay Dabral, David Dunning, Theodore Z. Schoenborn
  • Methods and apparatuses to effect a variable-width link
    Patent number: 7957428
    Abstract: Embodiments of the invention provide an algorithm for dividing a link into one or more reduced-width links. For one embodiment of the invention, a multiplexing scheme is employed to effect a bit transmission order required by a particular cyclic redundancy check. The multiplexed output bits are then swizzled on-chip to reduce on-board routing congestion.
    Type: Grant
    Filed: May 21, 2004
    Date of Patent: June 7, 2011
    Assignee: Intel Corporation
    Inventors: Maurice B. Steinman, Rahul R. Shah, Naveen Cherukuri, Aaron T. Spink, Allen J. Baum, Sanjay Dabral, Tim Frodsham, David S. Dunning, Theodore Z. Schoenborn
  • Providing error correction coding for probed data
    Patent number: 7917828
    Abstract: In one embodiment, the present invention includes a method for receiving an error correction code for information from a first port of a first agent and receiving the information from a second port of the first agent by probing a first link under test that couples the first agent and a second agent. The code may be used to validate the information, e.g., in a probe receiver during test or debug operations. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 28, 2006
    Date of Patent: March 29, 2011
    Assignee: Intel Corporation
    Inventors: Larry Tate, Richard Glass, Sanjay Dabral, Colin Looi
  • Circuit board including stubless signal paths and method of making same
    Patent number: 7907418
    Abstract: A circuit board may include first and second sides, a plurality of circuit board layers between the sides, and a plurality of signal traces located in respective circuit board layers. The circuit board layers and the signal traces may extend from a first component connection region at the first side of the circuit board to a second component connection region at the first side of the circuit board. The signal traces may thus form stubless signal paths through the circuit board between the component connection regions. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.
    Type: Grant
    Filed: December 1, 2009
    Date of Patent: March 15, 2011
    Assignee: Intel Corporation
    Inventors: Pascal Meier, Sanjay Dabral
  • LINK POWER SAVINGS WITH STATE RETENTION
    Publication number: 20100330927
    Abstract: Methods and apparatus relating to link power savings with state retention are described. In one embodiment, one or more components of two agents coupled via a serial link are turned off during idle periods while retaining link state in each agent. Other embodiments are also disclosed.
    Type: Application
    Filed: June 30, 2009
    Publication date: December 30, 2010
    Inventors: Naveen Cherukuri, Jeffrey Wilcox, Venkatraman Iyer, Selim Bilgin, David D. Dunning, Robin Tim Frodsham, Theodore Z. Schoenborn, Sanjay Dabral
  • Method for identifying bad lanes and exchanging width capabilities of two CSI agents connected across a link
    Patent number: 7844767
    Abstract: A technique is described by which two link agents with ports coupled together using a point-to-point interconnect in a system exchange their link width support capabilities and negotiate a link width that is mutually agreeable. The interconnect between each pair of agents comprises a pair of uni-directional links having multiple electrical wires, or lanes, where one link is used by a first agent to transmit data to a second agent and another link is used by the second agent to transmit data to the first agent.
    Type: Grant
    Filed: May 21, 2004
    Date of Patent: November 30, 2010
    Assignee: Intel Corporation
    Inventors: Naveen Cherukuri, Sanjay Dabral, David S. Dunning, Tim Frodsham, Theodore Z. Schoenborn, Rahul R. Shah, Maurice B. Steinman
  • Method and system for response determinism by synchronization
    Patent number: 7804890
    Abstract: A discussion of improving integrated device deterministic response to test vectors. For example, limiting the transmission delay for an integrated device's response within known bounds by synchronizing an initialization training sequence to a reset deassertion. Specifically, the proposal facilitates response determinism from the DUT by synchronizing training sequences and subsequently synchronizing flit transmission to reset assertion as sampled by reference clock.
    Type: Grant
    Filed: June 23, 2005
    Date of Patent: September 28, 2010
    Assignee: Intel Corporation
    Inventors: Muraleedhara H. Navada, Tim Frodsham, Sanjay Dabral, Allen Baum, Chris D. Matthews, Chris C. Gianos, Rahul R. Shah, Theodore Z. Schoenborn
  • Technique to create link determinism
    Patent number: 7747888
    Abstract: A technique for promoting determinism among bus agents within a point-to-point (PtP) network. More particularly, embodiments of the invention relate to techniques to compensate for link latency, data skew, and clock shift within a PtP network of common system interface (CSI) bus agents.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: June 29, 2010
    Assignee: Intel Corporation
    Inventors: Tim Frodsham, Michael J. Tripp, David J. O'Brien, Muraleedhara Navada, Naveen Cherukuri, Sanjay Dabral, David S. Dunning, Theodore Z. Schoenborn
  • Method, system, and apparatus for loopback parameter exchange
    Patent number: 7746795
    Abstract: A loopback test to test a communication link for a layered interface where in a master agent programs the electrical parameters for the slave agent, such as, the offset, timing, and current compensation with a loopback control register.
    Type: Grant
    Filed: July 23, 2004
    Date of Patent: June 29, 2010
    Assignee: Intel Corporation
    Inventors: Tim Frodsham, Naveen Cherukuri, Sanjay Dabral, David S. Dunning, Theodore Z. Schoenborn, Lakshminarayan Krishnamurty
  • Serial link apparatus, method, and system
    Patent number: 7711939
    Abstract: A source terminated serial link can recover from a low power mode by turning on multiple current-mode drivers in a phased sequence where the phased sequence is related to a resonant characteristic of a power supply net.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: May 4, 2010
    Assignee: Intel Corporation
    Inventors: Karthisha S. Canagasaby, Ken Drottar, David S. Dunning, Sanjay Dabral
  • Method and apparatus for acknowledgement-based handshake mechanism for interactively training links
    Patent number: 7711878
    Abstract: A method and apparatus for advancing initialization messages when initializing an interface is presented. In one embodiment, one of a sequence of training sequence messages are sent in serial mode across the data lanes of a generally-parallel interface between two agents. When one agent correctly receives a fixed number of messages, it may begin sending its messages with an acknowledgement. Thereafter, when that agent correctly receives a fixed number of messages including an acknowledgement, that agent may advance to sending the next training sequence messages in the sequence.
    Type: Grant
    Filed: May 21, 2004
    Date of Patent: May 4, 2010
    Assignee: Intel Corporation
    Inventors: Naveen Cherukuri, Sanjay Dabral, David S. Dunning, Tim Frodsham, Theodore Z. Schoenborn
  • REDUNDANT ACKNOWLEDGMENT IN LOOPBACK ENTRY
    Publication number: 20100103826
    Abstract: Redundant acknowledgment between agents performing a loopback test over bidirectional communications bus is described. In one example, in a processor including a communications agent coupled to a bidirectional communications bus, the communications agent initiates loopback communications to a second agent, sends a packet including a redundant acknowledgment sequence to the second agent, receives the packet including the redundant acknowledgement sequence looped back from the second agent, determines whether the received redundant acknowledgment sequence is valid, sends a test sequence to the second agent, receives the test sequence looped back, and if the received redundant acknowledgment sequence is determined to be valid, then checks the received test sequence.
    Type: Application
    Filed: December 30, 2009
    Publication date: April 29, 2010
    Inventors: Tim Frodsham, Zale Schoenborn, Sanjay Dabral, Muraleedhara Navada
  • I/O Link with configurable forwarded and derived clocks
    Publication number: 20100098201
    Abstract: An electronic communications receiver includes a derived clock signal circuit operable to receive a data signal and to derive a derived clock signal from the received data signal. A separate forwarded clock signal circuit is further operable to receive a forwarded clock signal, and a clock management circuit is operable to receive signals from the derived clock signal circuit and the forwarded clock signal circuit, and to output an output clock signal.
    Type: Application
    Filed: December 1, 2009
    Publication date: April 22, 2010
    Inventors: Karthisha S. Canagasaby, Sanjay Dabral