Abstract: A flip-chip semiconductor device with generic bump patterns formed on a semiconductor substrate and having optimized electrical performance is provided. In a preferred embodiment, the flip-chip semiconductor device includes a semiconductor substrate on which active elements are formed and which has a surface having a plurality of peripheral portions, the active elements including Input/Output (I/O) circuitry and logic circuitry, a first power supply wiring and a first ground wiring disposed in the semiconductor substrate, a signal wiring disposed in the semiconductor substrate, and a first plurality of bumps arranged on the plurality of peripheral portions and selectively used for coupling the semiconductor substrate to a second substrate. The first plurality of bumps are arranged in a matrix pattern of 6 rows by n columns. Bumps in predetermined locations in the matrix are selectively coupled to the first power supply wiring and the first ground wiring.

Abstract: A circuit arrangement for interconnecting electronic components such as integrated circuit devices, chip packages and/or circuit boards includes signal, first fixed potential (e.g., power) and second fixed potential (e.g., ground) interconnects arranged into an interconnection layout pattern that offers greater flexibility, performance and cost effectiveness than conventional patterns. In some implementations, the interconnection layout pattern incorporates one or more tiles of interconnects, with each tile defining a plurality of interconnect positions arranged into at least three rows and at least four columns. For each tile, a signal interconnect is disposed at each of the three interconnect positions in each of the first and fourth columns, and one each of a signal interconnect, a first fixed potential interconnect and a second fixed potential interconnect are disposed in each of the second and third columns.

Abstract: Improved manufacturability, yield, and reliability are achieved during wirebonding of a semiconductor die of reduced size by employing two rows of staggered conductive connectors, or bond pads, for wirebonding the die to a semiconductor package. An outer row of conductive connectors is positioned closer to the edge of the die than an inner row of conductive connectors and includes a greater number of connectors than the inner row. The die can be wirebonded to a package substrate having either a single row of bondfingers or multiple rows of bondfingers. In one embodiment, bond wires attaching the inner row of conductive pad connectors to the package substrate have a greater loop height than bond wires attaching the outer row of conductive pad connectors to the package substrate.

Abstract: An integrated circuit having an outer ring of bonding pads which is positioned so as to be adjacent to and concentric with the perimeter of the integrated circuit. The outer ring of bonding pads extends for at least a first portion of the perimeter. An inner ring of bonding pads is positioned interior of, adjacent to, and concentric with the first ring of bonding pads. The inner ring of bonding pads extends for at least a second portion of the perimeter. The first portion is greater than the second portion, or in other words, the outer ring of bonding pads extends further around the integrated circuit than the inner ring of bonding pads. In addition, the outer ring of bonding pads has a greater number of bonding pads that the inner ring of bonding pads. Traces are electrically connected to the bonding pads of the inner and outer rings, such that each pad is electrically connected to a unique trace, meaning that each pad has a trace which is associated with just that pad and with no other pad.

Abstract: A surface-mount ball-grid array package is provided for an integrated circuit assembly. The ball-grid array package has a circuit chip recess through which vias extend to open on a bottom surface of the package. A peripheral portion of the package is defined around the vias formed in the recess, and an integrated circuit die is seated within this peripheral portion. During manufacture, the package is held on a vacuum chuck by applying vacuum to the peripheral portion of the package. An adhesive material is placed in the recess to extend partially through the vias. The circuit chip is thereafter disposed in the recess on the adhesive material to complete the fabrication process. Ambient air is communicated to the vias on the bottom surface of the package to prevent the adhesive from being pulled through the vias by the applied vacuum.

Abstract: A method of making a surface-mount technology plastic-package ball-grid array integrated circuit assembly. According to the method, a surface-mount ball-grid array package is provided for an integrated circuit assembly. The array package has a circuit chip recess through which vias extend, opening on a bottom surface of the array package. A peripheral portion of the array package is defined around the vias formed in the recess. The array package is held on a vacuum chuck by applying vacuum to the peripheral portion of package. An adhesive material is then placed in the recess to extend partially through the vias. A circuit chip is finally disposed in the recess on the adhesive material to complete the fabrication process. Substantially ambient pressure is communicated to the vias on the bottom surface of the array package to prevent the adhesive from being pulled through the vias by the applied vacuum.

Abstract: A semiconductor device package for one or more semiconductor dice having core circuits and input-output circuits uses a package substrate having one pair of biplanar conductive planes and another pair of biplanar conductive planes. The pairs of planes are positioned in a coplanar relationship between the package substrate top surface and bottom surface. The top surface has lands connected to the conductive planes and to the power bond pads for the core circuits and input-output circuits on the semiconductor die. The top surface has many top traces connected to the signal bond pads on the semiconductor die. The package substrate may have a die paddle connected to one land and/or thermal vias to conduct heat away from the semiconductor die. Power may be supplied to die core circuits through one pair of planes and to die input-output circuits through another pair of planes to decouple the core circuits from the input-output circuits and minimize noise induced false switching in either set of circuits.