Abstract: A method, system and computer program product for controlling access to data files stored in a repository is disclosed. The method includes receiving a request for a data file from a requester. The request specifies a data format preference for receiving the data file. The requested data format is different than either of a data format used to create the data file and a data format in which the data file is stored at the time of the request. The method also includes determining if the requester is authorized to access the requested data file and translating the requested data file from a stored data format into the requested data format responsive to receiving the request if the stored format differs from the requested format. The method further includes making the translated data file accessible to the requester if it is determined that the requester is authorized.

Abstract: A system and method for test generation for system level verification using parallel algorithms are provided. The present invention generates test patterns for system level tests by exploiting the scalability of parallel algorithms while allowing for data set coloring and expected result checking. Based on the characteristics of the system being tested an iterative parallel algorithm is selected from a plurality of possible parallel algorithms. The selected parallel algorithm is then separated into separate program statements for execution by a plurality of processors. A serial version of the selected algorithm is executed to generate a set of expected results. The devised parallel version of the selected algorithm is then run to generate a set of test result data which is compared to the set of expected results. If the two sets of data match, it is determined that the system is operating correctly.

Abstract: An apparatus and method are provided in which a previously verified SoC is coupled to a SoC under test via a communication bus or other type of communication interface. The previously verified SoC is provided with the same test stimuli as the SoC under test and thus, generates expected test results data. The test stimuli are sent to the SoC under test via a peripheral communication interface between the previously verified SoC and the SOC under test. The SoC under test generates actual test result data that is output to the previously verified SoC. The previously verified SoC may then compare the expected test results data with the actual test result data generated by the SoC under test to determine if they match. If the two sets of data do not match, then a mismatch notification may be generated and output.

Abstract: A design structure is embodied in a machine readable medium for designing, manufacturing, or testing integrated circuitry. The design structure includes a general purpose computational resource for performing general purpose operations of a system. A special purpose computational resource is coupled to the general purpose computational resource. The special purpose computational resource is for: storing test patterns, a description of the integrated circuitry, and a description of hardware for testing the integrated circuitry; and executing software for simulating an operation of the described hardware's testing of the described integrated circuitry in response to the test patterns.

Abstract: A data storage device tracing system includes at least one container configured to maintain at least one electronic data storage device, a two-way radio coupled to each of the container(s), and a network including a network coordinator configured to transmit to and receive data from the two-way radio. In this regard, the two-way radio communicates real-time container location data to the network coordinator to enable real-time tracing of the container(s) and the electronic data storage device(s).

Abstract: A method is provided in which a previously verified SoC is coupled to a SoC under test via a communication bus or other type of communication interface. The previously verified SoC is provided with the same test stimuli as the SoC under test and thus, generates expected test results data. The test stimuli are sent to the SoC under test via a peripheral communication interface between the previously verified SoC and the SoC under test. The SoC under test generates actual test result data that is output to the previously verified SoC. The previously verified SoC may then compare the expected test results data with the actual test result data generated by the SoC under test to determine if they match. If the two sets of data do not match, then a mismatch notification may be generated and output.

Abstract: A buffer includes a source follower module and a pull-up/pull-down module that is connected to the source follower module. An output signal at the output terminal of the source follower module follows an input signal at the input terminal with a predetermined delay, independent of the Miller capacitance. The pull-up/pull-down module pulls the output of source follower to supply/ground rail.

Abstract: A general purpose computational resource is provided for performing general purpose operations of a system. A special purpose computational resource is coupled to the general purpose computational resource.

Abstract: A system and method for incorporating design behavior and external stimulus in microdevice model feedback using a shared memory is presented. The invention describe herein uses the attached memory model to provide additional heuristics to an application executing on an emulation system's device model, which results in a more detail and real-life device emulation. The attached memory model provides a storage area for a runtime software environment to store emulation data, which is subsequently provided to the device model during emulation. The emulation data may include 1) randomization stimuli to the device model, 2) additional runtime data for checking heuristics, and 3) emulation data points that are otherwise not accessible to the device model.

Abstract: An electronic data storage device tracing system includes at least one data storage device and a reader system. The data storage device includes a housing having an optical label and a device RFID tag coupled to the housing. In this regard, the optical label is printed with a VOLSER number and the device RFID tag includes a chip that electronically stores the VOLSER number. The reader system is configured to read the VOLSER number from the chip and trace the at least one data storage device entering/exiting the reader system.

Abstract: A buffer includes a source follower module and a pull-up/pull-down module that is connected to the source follower module. An output signal at the output terminal of the source follower module follows an input signal at the input terminal with a predetermined delay, independent of the Miller capacitance. The pull-up/pull-down module pulls the output of source follower to supply/ground rail.

Abstract: An electronic data storage device tracing system includes at least one data storage device and a reader system. The data storage device includes a housing having an optical label and a device RFID tag coupled to the housing. In this regard, the optical label is printed with a volser number and the device RFID tag includes a chip that electronically stores the volser number. The reader system is configured to read the volser number from the chip and trace the at least one data storage device entering/exiting the reader system.

Abstract: A method for increasing performance of non-relational databases with reduction in view index sizes is provided. One or more user views are provided in addition to the master view having all hierarchical/categorized data. User views are created having a subset of this hierarchical/categorized data that significantly reduces index size and improves performance. The indexes of the user view are associated with the indexes of the master view. This method improves view caching by dividing view cache into partitions based on the types of view, each with different priorities and management techniques. The master view may have a higher priority and may be used by servers while the user view may have lower priorities and may be used by users and client applications. In this way, legacy non-relational databases may continue to be suitably maintained with acceptable performance and avoiding potential cost and risk of migrating to a relational database.

Abstract: A method for increasing performance of non-relational databases with reduction in view index sizes is provided. One or more user views are provided in addition to the master view having all hierarchical/categorized data. User views are created having a subset of this hierarchical/categorized data that significantly reduces index size and improves performance. The indexes of the user view are associated with the indexes of the master view. This method improves view caching by dividing view cache into partitions based on the types of view, each with different priorities and management techniques. The master view may have a higher priority and may be used by servers while the user view may have lower priorities and may be used by users and client applications. In this way, legacy non-relational databases may continue to be suitably maintained with acceptable performance and avoiding potential cost and risk of migrating to a relational database.

Abstract: A system and method for test generation for system level verification using parallel algorithms are provided. The present invention generates test patterns for system level tests by exploiting the scalability of parallel algorithms while allowing for data set coloring and expected result checking. Based on the characteristics of the system being tested an iterative parallel algorithm is selected from a plurality of possible parallel algorithms. The selected parallel algorithm is then separated into separate program statements for execution by a plurality of processors. A serial version of the selected algorithm is executed to generate a set of expected results. The devised parallel version of the selected algorithm is then run to generate a set of test result data which is compared to the set of expected results. If the two sets of data match, it is determined that the system is operating correctly.

Abstract: A system is described for managing interaction between an untimed HAL portion and a timed HDL portion of the testbench, wherein the timed portion is embodied on an emulator and the un-timed portion executes on a workstation. Repeatability of verification results may be achieved even though the HAL portion and the HDL portion run in parallel with each other. A communication interface is also described for synchronizing and passing data between multiple HDL threads on the emulator domain and simultaneously-running multiple HAL threads on the workstation domain. In addition, a remote procedural-call-based communication link, transparent to the user, is generated between the workstation and the emulator. A technique provides for repeatability for blocking and non-blocking procedure calls. FSMs and synchronization logic are automatically inferred to implement remote procedural calls. A subset of behavioral language is identified that combines the power of conventional modeling paradigms with RTL performance.

Abstract: A system and method for test generation for system level verification using parallel algorithms are provided. The present invention generates test patterns for system level tests by exploiting the scalability of parallel algorithms while allowing for data set coloring and expected result checking. Based on the characteristics of the system being tested an iterative parallel algorithm is selected from a plurality of possible parallel algorithms. The selected parallel algorithm is then separated into separate program statements for execution by a plurality of processors. A serial version of the selected algorithm is executed to generate a set of expected results. The devised parallel version of the selected algorithm is then run to generate a set of test result data which is compared to the set of expected results. If the two sets of data match, it is determined that the system is operating correctly.

Abstract: Techniques for establishing TTR indication in ADSL Annex C based communication systems are disclosed. The techniques enable, for example, hyperframe alignment and synchronized initialization procedures (e.g., G.hs).

Abstract: A system and method is presented for synthesizing both a design under test (DUT) and its test environment (i.e., the testbench for the DUT), into an equivalent structural model suitable for execution on a reconfigurable hardware platform. This may be achieved without any change in the existing verification methodology. Behavioral HDL may be translated into a form that can be executed on a reconfigurable hardware platform. A set of compilation transforms are provided that convert behavioral constructs into RTL constructs that can be directly mapped onto an emulator. Such transforms are provided by introducing the concepts of a behavioral clock and a time advance finite state machine (FSM) that determines simulation time and sequences concurrent computing blocks in the DUT and the testbench.

Abstract: A mobile station (323) may register with a base set (301) to access a fixed line service, such as broadband IP network (315), to make and receive calls. When the mobile station (323) is within a radio coverage area of access point (313), it may seamlessly register itself and receive calls placed to a home phone number. Mobile station (323) may initiate a call using either its own MSISDN of the MSISDN of the base set (301), but not both. A second mobile station (327) registered with base set (301) may participate in the same call, acting as an extension line. In this manner, home base (301) provides a user cordless phone experience similar to having cordless extension phones connected to a PSTN line.