Abstract: A more efficient network can be achieved by leveraging an adaptive dejitter buffer. The dejitter buffer can be dynamically adjusted based off a network data analysis. A communication handover can be adjusted or shifted based on voice inactivity data related to a forecasted punctuation. The dejitter buffer memory/depth of a mobile device can also be adjusted in accordance with receiving a delay interruption length associated with another mobile device. Thereafter, the dejitter buffer memory can be filled with voice packet data to decrease a packet delay variation at the mobile device.

Abstract: Flexible interconnects, flexible integrated circuit systems and devices, and methods of making and using flexible integrated circuitry are presented herein. A flexible integrated circuit system is disclosed which includes first and second discrete devices that are electrically connected by a discrete flexible interconnect. The first discrete devices includes a first flexible multi-layer integrated circuit (IC) package with a first electrical connection pad on an outer surface thereof. The second discrete device includes a second flexible multi-layer integrated circuit (IC) package with a second electrical connection pad on an outer surface thereof. The discrete flexible interconnect is attached to and electrically connects the first electrical connection pad of the first discrete device to the second electrical connection pad of the second discrete device.

Abstract: A wireless battery charging system includes an inductive receiving member for receiving an AC signal for output to a matching circuit having a variable impedance with variable matching parameters. The output of the matching circuit drives a rectifier circuit for converting the inputted AC signal to a first DC voltage and having variable rectifier parameters to vary the voltage drop thereacross. A DC-to-DC converter for converting the first DC voltage to a regulated voltage for charging the battery. A current sensor senses current through the inductive receiving member, rectifier circuit and DC-to-DC converter. A controller senses the voltage drop across each of the matching circuit, rectifier circuit and DC-to-DC converter and the current there through to determine power dissipation in each of the matching circuit, rectifier circuit and DC-to-DC converter. The power distribution in each of the matching circuit, the rectifier circuit and the DC-to-DC converter can then be varied.

Abstract: A system includes a non-transitory memory and one or more hardware processors configured to read instructions from the non-transitory memory to perform operations. The operations include maintaining a list of agent profiles, wherein each of the agent profiles comprises a plurality of skills toward which points are awarded based on completed activities, receiving a service request, identifying one or more skills associated with the service request, referencing the list of agent profiles to identify one of the agent profiles possessing the one or more skills associated with the service request, and assigning the service request to the agent profile possessing the one or more skills associated with the service request.

Abstract: A system includes a non-transitory memory and one or more hardware processors configured to read instructions from the non-transitory memory.

Abstract: A configurable driver integrated circuit is disclosed having a plurality of input/output terminals for interfacing exterior of the integrated circuit. The integrated circuit includes a plurality of driver circuits, with each driver circuit including a transistor having a source and a drain, and each of the source and drain thereof connected to a dedicated and respective one of the input/output terminals and further includes a gate driver for driving a gate of the transistor, with supply inputs associated with a floating voltage domain, and each driver circuit also includes a level shift circuit for shifting the level of a logic signal from a fixed voltage domain to the floating voltage domain. A switching circuitry generates switching signals in a fixed voltage domain for controlling the operation of each of the driver circuits in accordance with a predetermined configuration defined by external circuit.

Abstract: The present application is directed towards systems and methods for providing user interfaces for management applications via a definition-based graphical user interface (GUI) framework for developing web based management applications for servers, intermediaries, routers, wide area network (WAN) accelerators, caches, switches, or any other type and form of computing device. The plug-in free framework reduces the server's resource consumption and bandwidth by making a full use of resources available on the client computing device or browser. A complete web application can be developed using JavaScript Object Notation (JSON) definitions along with a representational state transfer (REST) based application programming interface (API) efficiently using the framework, which may comprise light-weight pure JavaScript or similar executable code. In many embodiments, the framework may be layered in a model-view-controller (MVC) architecture easing resource consumption, maintenance and extensibility.

Abstract: A more efficient network can be achieved by leveraging an adaptive dejitter buffer. The dejitter buffer can be dynamically adjusted based off a network data analysis. A communication handover can be adjusted or shifted based on voice inactivity data related to a forecasted punctuation. The dejitter buffer memory/depth of a mobile device can also be adjusted in accordance with receiving a delay interruption length associated with another mobile device. Thereafter, the dejitter buffer memory can be filled with voice packet data to decrease a packet delay variation at the mobile device.

Abstract: Techniques of this disclosure may include processing one or more regions-of-interest (ROI) of an input image through a model of a display processor, calculating a first data integrity check value on the one or more ROI of the input image after processing through the model, processing the input image by the display processor, calculating a second data integrity check value on the one or more ROI by the display processor after the display processor processes the input image, comparing the first data integrity check value to the second data integrity check value, and generating an interrupt if the comparison indicates that the first data integrity check value and the second data integrity check value do not match.

Abstract: A system may include a processor that receives tasks to be performed, determines ordering rules associated with the tasks, and identifies a first set of employees to perform the one or more tasks based on schedule data associated with the employees and the ordering rules. The processor may then identify one employee of the first set of employees to perform the tasks based on a current schedule for the one employee and the ordering rules, identify scheduled tasks to remove from the current schedule based on un-assignment rules, and generate an adjusted current schedule to include the tasks and remove the scheduled tasks from the current schedule. The processor may then send a notification indicative of an adjusted current schedule to a computing device associated with the one employee.

Abstract: A configurable driver integrated circuit is disclosed having a plurality of input/output terminals for interfacing exterior of the integrated circuit. The integrated circuit includes a plurality of driver circuits, with each driver circuit including a transistor having a source and a drain, and each of the source and drain thereof connected to a dedicated and respective one of the input/output terminals and further includes a gate driver for driving a gate of the transistor, with supply inputs associated with a floating voltage domain, and each driver circuit also includes a level shift circuit for shifting the level of a logic signal from a fixed voltage domain to the floating voltage domain. A switching circuitry generates switching signals in a fixed voltage domain for controlling the operation of each of the driver circuits in accordance with a predetermined configuration defined by external circuit.

Abstract: Flexible integrated circuit (IC) modules, flexible IC devices, and methods of making and using flexible IC modules are presented herein. A flexible integrated circuit module is disclosed which includes a flexible substrate and a semiconductor die attached to the flexible substrate. An encapsulating layer, which is attached to the flexible substrate, includes a thermoplastic resin and/or a polyimide adhesive encasing therein the semiconductor die. The encapsulating layer may be an acrylic-based thermally conductive and electrically isolating polyimide adhesive. Optionally, the encapsulating layer may be a B-stage FR-4 glass-reinforced epoxy thermoplastic polymer or copolymer or blend. The die may be embedded between two flexible substrates, each of which includes a layer of flexible polymer, such as a polyimide sheet, with two layers of conductive material, such as copper cladding, disposed on opposing sides of the layer of flexible polymer.

Abstract: A wireless battery charging system includes an inductive receiving member for receiving an AC signal for output to a matching circuit having a variable impedance with variable matching parameters. The output of the matching circuit drives a rectifier circuit for converting the inputted AC signal to a first DC voltage and having variable rectifier parameters to vary the voltage drop thereacross. A DC-to-DC converter for converting the first DC voltage to a regulated voltage for charging the battery. A current sensor senses current through the inductive receiving member, rectifier circuit and DC-to-DC converter. A controller senses the voltage drop across each of the matching circuit, rectifier circuit and DC-to-DC converter and the current there through to determine power dissipation in each of the matching circuit, rectifier circuit and DC-to-DC converter. The power distribution in each of the matching circuit, the rectifier circuit and the DC-to-DC converter can then be varied.

Abstract: A more robust and efficient flow of voice or other content packets can be achieved by leveraging an adaptive dejitter buffer. The dejitter buffer can be dynamically adjusted according to network conditions including handover. The dejitter buffer memory/depth can be adjusted in accordance with a delay interruption length associated with various handover types. Thereafter, the dejitter buffer memory can be filled with packet data to decrease a packet delay variation associated with handover.

Abstract: Techniques of this disclosure may include processing one or more regions-of-interest (ROI) of an input image through a model of a display processor, calculating a first data integrity check value on the one or more ROI of the input image after processing through the model, processing the input image by the display processor, calculating a second data integrity check value on the one or more ROI by the display processor after the display processor processes the input image, comparing the first data integrity check value to the second data integrity check value, and generating an interrupt if the comparison indicates that the first data integrity check value and the second data integrity check value do not match.

Abstract: A more robust and efficient flow of voice or other content packets can be achieved by leveraging an adaptive dejitter buffer. The dejitter buffer can be dynamically adjusted according to network conditions including handover. The dejitter buffer memory/depth can be adjusted in accordance with a delay interruption length associated with various handover types. Thereafter, the dejitter buffer memory can be filled with packet data to decrease a packet delay variation associated with handover.

Abstract: Aspects of the disclosed technology relate to techniques for corrupting memories in emulation. After a power domain in a circuit design being emulated in an emulator is powered down, a main memory model for a memory in the power domain is corrupted and a cache memory model for the memory is invalidated. The cache memory model is a hardware model in the emulator and the main memory model is a software model in a workstation coupled to the emulator. The cache memory model stores a subset of data that are stored in the main memory model. The combination of the main memory model and the cache memory model is used to model the memory.

Abstract: This disclosure relates generally to information security, and more particularly to implementation and management of information security of a Big Data environment of an organization. In one embodiment, security related inputs are received from a user and are converted into security requirement. Thereafter, a security policy template is identified from plurality of pre-defined security policy templates based on security reference architecture and the security requirement. The security policy template represents a plurality of security controls. Thereafter, one or more security controls are selected from the security controls based on the security requirement. Further, one or more existing security controls implemented in Big Data environment are identified. Thereafter, the selected security controls are compared with the existing security controls for determining a security control that is not implemented in the Big Data environment.

Abstract: Aspects of the disclosed technology relate to techniques of design implementation for FPGA prototyping. An initial FPGA-mapped netlist and a generic RTL design associated with the initial FPGA-mapped netlist are generated based on an original RTL (register-transfer level) design for a circuit design and optionally on verification-related features. Based on the initial FPGA-mapped netlist, the circuit design is partitioned into design partitions for implementing the circuit design across a plurality of FPGA chips. Final FPGA-mapped netlists are then generated based on the design partitions represented by the generic RTL design or by a combination of the generic RTL design and the initial FPGA-mapped netlist.