Abstract: Structures and techniques for restraining devices for testing. Test sockets may retain devices under test using one or more retention members protruding from sidewalls of the test sockets. Retained devices may be oriented such that contact arms may traverse horizontally to access the devices to, for example, provide desired testing environments. Devices may be retained by forces applied by the retention members to the retained devices in response to displacement, such as compression or deformation, of the retention members caused by the retained devices. Retention of the devices may be achieved without the need for additional fasteners, claims, or adjustment.

Abstract: Structures and techniques for restraining devices for testing. Test sockets may retain devices under test using one or more retention members protruding from sidewalls of the test sockets. Retained devices may be oriented such that contact arms may traverse horizontally to access the devices to, for example, provide desired testing environments. Devices may be retained by forces applied by the retention members to the retained devices in response to displacement, such as compression or deformation, of the retention members caused by the retained devices. Retention of the devices may be achieved without the need for additional fasteners, claims, or adjustment.

Abstract: A control apparatus for a computer is described that includes an arbiter circuit for selecting a first controller for supplying the memory of the computer with a first plurality of addresses from a first bus at a first rate and for selecting the second controller for supplying the memory of the computer with a second plurality of addresses from a second bus at a second rate. The first and second controllers are selected such that the first and second controllers do not supply the memory with more than one memory address at a time. A method for controlling the use of a computer bus is also described. A plurality of requests to use the bus are received. A length of a first period for use of the bus and a length of a second period for use of the bus are preselected. Each of the plurality of requests are granted.

Abstract: A control apparatus for a computer is described that includes an arbiter circuit for selecting a first controller for supplying the memory of the computer with a first plurality of addresses from a first bus at a first rate and for selecting the second controller for supplying the memory of the computer with a second plurality of addresses from a second bus at a second rate. The first and second controllers are selected such that the first and second controllers do not supply the memory with more than one memory address at a time. A method for controlling the use of a computer bus is also described. A plurality of requests to use the bus are received. A length of a first period for use of the bus and a length of a second period for use of the bus are preselected. Each of the plurality of requests are granted.

Abstract: A one-chip, integrated-circuit, microprogram sequence controller for use in a microprogrammed system having a data processing unit and a microprogram memory, that controls the order and execution of microinstructions within the microprogram memory. The controller is provided with two 16-bit microinstruction address input busses and a 16-bit output bus on which microinstruction addresses are issued to the microprogram memory. One of the input busses and the output busses are bidirectional providing access to various on-chip parameters such as the contents of the top of an on-chip stack memory or the value of an on-chip stack pointer. An on-chip comparator permits trapping of a microinstruction at a specified address or gathering of run-time statistics. A structured, 64-element instruction set is provided which includes sixteen special-function continue instructions which perform additional operations without imposing added time requirements.

Abstract: A one-chip, integrated-circuit, 32-bit bipolar arithmetic-logic unit (ALU) capable of performing complex operations on selected one, two, three, or four 8-bit bytes or selected contiguous bits of the operands in a single clock cycle. The ALU has three 32-bit inputs consisting of two data word operands and a mask; operand with shifters provided at one of the operand input, the mask input and at the ALU output so that three operands can be simultaneously received, shifted, masked, combined, and the result shifted in a single instruction cycle. Bit positions which are not selected to take part in an ALU operation pass unaffected to the outputs from one of the data word inputs. A swap multiplexer is present at the data word inputs to afford interchanging of these inputs before processing by the ALU.