Patents by Inventor Sanjay K. KUMAR

Sanjay K. KUMAR has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200319913
    Abstract: In one embodiment, an apparatus includes an input/output virtualization (IOV) device comprising: at least one function circuit to be shared by a plurality of virtual machines (VMs); and a plurality of assignable device interfaces (ADIs) coupled to the at least one function circuit, wherein each of the plurality of ADIs is to be associated with one of the plurality of VMs and comprises a first process address space identifier (PASID) field to store a first PASID to identify a descriptor queue stored in a host address space and a second PASID field to store a second PASID to identify a data buffer located in a VM address space. Other embodiments are described and claimed.
    Type: Application
    Filed: June 23, 2020
    Publication date: October 8, 2020
    Inventors: SANJAY K. KUMAR, RAJESH SANKARAN, UTKARSH Y. KAKAIYA, PRATIK M. MAROLIA
  • Publication number: 20200226066
    Abstract: An apparatus is described. The apparatus includes a memory controller to interface with a multi-level memory having a near memory and a far memory. The memory controller to maintain first and second caches. The first cache to cache pages recently accessed from the far memory. The second cache to cache addresses of pages recently accessed from the far memory. The second cache having a first level and a second level. The first level to cache addresses of pages that are more recently accessed than pages whose respective addresses are cached in the second level. The memory controller comprising logic circuitry to inform system software that: a) a first page in the first cache that is accessed less than other pages in the first cache is a candidate for migration from the far memory to the near memory; and/or, b) a second page whose address travels a threshold number of round trips between the first and second levels of the second cache is a candidate for migration from the far memory to the near memory.
    Type: Application
    Filed: March 27, 2020
    Publication date: July 16, 2020
    Inventors: Eran SHIFER, Zeshan A. CHISHTI, Sanjay K. KUMAR, Zvika GREENFIELD, Philip LANTZ, Eshel SERLIN, Asaf RUBINSTEIN, Robert J. ROYER, JR.
  • Publication number: 20200104780
    Abstract: The disclosed embodiments provide a system for processing a query for a ranking of candidates for an opportunity. During operation, the system obtains parameters associated with a query for a ranking of candidates for an opportunity, wherein the parameters include a candidate and the opportunity. Next, the system matches one or more of the parameters to a fixed number of quantile thresholds calculated from a distribution of scores for the candidates. The system then estimates, based on the fixed number of quantile thresholds, a quantile for a score of the candidate. Finally, the system outputs a position of the candidate within the ranking based on the estimated quantile.
    Type: Application
    Filed: September 27, 2018
    Publication date: April 2, 2020
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Sanjay Sachdev, Arjun K. Kulothungun, Rohan Ramanath, Deepak Dileep Kumar
  • Patent number: 10402335
    Abstract: In one embodiment, an apparatus comprises a memory to store executable instructions of an operating system and a processor to identify a request for data from an application; determine whether a persistent page cache stores a copy of the data, wherein the persistent page cache is directly addressable by the processor and is to cache data of a storage device that is not directly addressable by the processor; and access the data from the persistent page cache.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: September 3, 2019
    Assignee: Intel Corporation
    Inventors: Sanjay K. Kumar, Dheeraj R. Subbareddy, Jeffrey R. Jackson
  • Publication number: 20190114196
    Abstract: Examples include a method of live migrating a virtual device by creating a virtual device in a virtual machine, creating first and second interfaces for the virtual device, transferring data over the first interface, detecting a disconnection of the virtual device from the virtual machine, switching data transfers for the virtual device from the first interface to the second interface, detecting a reconnection of the virtual device to the virtual machine, and switching data transfers for the virtual device from the second interface to the first interface.
    Type: Application
    Filed: December 6, 2018
    Publication date: April 18, 2019
    Inventors: Mitu AGGARWAL, Nrupal JANI, Manasi DEVAL, Kiran PATIL, Parthasarathy SARANGAM, Rajesh M. SANKARAN, Sanjay K. KUMAR, Utkarsh Y. KAKAIYA, Philip LANTZ, Kun TIAN
  • Publication number: 20190114194
    Abstract: Examples may include a method of instantiating a virtual machine; instantiating a virtual device to transmit data to and receive data from assigned resources of a shared physical device by receiving input data requesting assigned resources for the virtual device, allocating assigned resources to the virtual device based at least in part on the input data, and mapping a page location in an address space of the shared physical device for a selected one of the assigned resources to a page location in a memory-mapped input/output (MMIO) space of the virtual device; and assigning the virtual device to the virtual machine, the virtual machine to transmit data to and receive data from the physical device via the MMIO space of the virtual device.
    Type: Application
    Filed: December 6, 2018
    Publication date: April 18, 2019
    Inventors: Nrupal JANI, Manasi DEVAL, Anjali SINGHAI, Parthasarathy SARANGAM, Mitu AGGARWAL, Neerav PARIKH, Alexander H. DUYCK, Kiran PATIL, Rajesh M. SANKARAN, Sanjay K. KUMAR, Utkarsh Y. KAKAIYA, Philip LANTZ, Kun TIAN
  • Publication number: 20190114283
    Abstract: Examples may include a computing platform having a host driver to get a packet descriptor of a received packet stored in a receive queue and to modify the packet descriptor from a first format to a second format. The computing platform also includes a guest virtual machine including a guest driver coupled to the host driver, the guest driver to receive the modified packet descriptor and to read a packet buffer stored in the receive queue using the modified packet descriptor, the packet buffer corresponding to the packet descriptor.
    Type: Application
    Filed: December 6, 2018
    Publication date: April 18, 2019
    Applicants: Intel Corporation, Intel Corporation
    Inventors: Manasi DEVAL, Nrupal JANI, Anjali SINGHAI, Parthasarathy SARANGAM, Mitu AGGARWAL, Neerav PARIKH, Kiran PATIL, Rajesh M. SANKARAN, Sanjay K. KUMAR, Utkarsh Y. KAKAIYA, Philip LANTZ, Kun TIAN
  • Publication number: 20190114195
    Abstract: Examples may include a method of instantiating a virtual machine, instantiating a virtual device to transmit data to and receive data from assigned resources of a shared physical device; and assigning the virtual device to the virtual machine, the virtual machine to transmit data to and receive data from the physical device via the virtual device.
    Type: Application
    Filed: December 6, 2018
    Publication date: April 18, 2019
    Inventors: Nrupal JANI, Manasi DEVAL, Anjali SINGHAI, Parthasarathy SARANGAM, Mitu AGGARWAL, Neerav PARIKH, Alexander H. DUYCK, Kiran PATIL, Rajesh M. SANKARAN, Sanjay K. KUMAR, Utkarsh Y. KAKAIYA, Philip LANTZ, Kun TIAN
  • Publication number: 20190107965
    Abstract: Examples may include a method of protecting memory and I/O transactions. The method includes allocating memory for an application, assigning a resource of a physical device to the application, assigning a process address space identifier to the assigned resource, creating a security enclave to protect the allocated memory of the application, and associating the security enclave with the process address space identifier to protect the allocated memory and the assigned resource.
    Type: Application
    Filed: December 6, 2018
    Publication date: April 11, 2019
    Inventors: Manasi DEVAL, Nrupal JANI, Parthasarathy SARANGAM, Mitu AGGARWAL, Kiran PATIL, Rajesh M. SANKARAN, Sanjay K. KUMAR, Utkarsh Y. KAKAIYA, Philip LANTZ, Kun TIAN
  • Publication number: 20190108106
    Abstract: Examples include a method of performing failover of in an I/O architecture by allocating a first set of resources, associated with a first port of a physical device, to a virtual device, allocating a second set of resources, associated with a second port of the physical device, to the virtual device, assigning the virtual device to a virtual machine, activating the first set of resources, and transferring data between the virtual machine and the first port using the virtual device and the first set of resources. The method further includes detecting an error in the first set of resources, deactivating the first set of resources and activating the second set of resources, and transferring data between the virtual machine and the second port using the virtual device and the second set of resources.
    Type: Application
    Filed: December 6, 2018
    Publication date: April 11, 2019
    Inventors: Mitu AGGARWAL, Nrupal JANI, Manasi DEVAL, Kiran PATIL, Parthasarathy SARANGAM, Rajesh M. SANKARAN, Sanjay K. KUMAR, Utkarsh Y. KAKAIYA, Philip LANTZ, Kun TIAN
  • Publication number: 20180285276
    Abstract: In one embodiment, an apparatus comprises a memory to store executable instructions of an operating system and a processor to identify a request for data from an application; determine whether a persistent page cache stores a copy of the data, wherein the persistent page cache is directly addressable by the processor and is to cache data of a storage device that is not directly addressable by the processor; and access the data from the persistent page cache.
    Type: Application
    Filed: March 31, 2017
    Publication date: October 4, 2018
    Applicant: Intel Corporation
    Inventors: Sanjay K. Kumar, Dheeraj R. Subbareddy, Jeffrey R. Jackson
  • Patent number: 9880932
    Abstract: A processor includes a memory management unit and a front end including a decoder. The decoder includes logic to receive a flush-on-commit (FoC) instruction to flush dirty data from a volatile cache to a persistent memory upon commitment of a store associated with the FoC instruction. The memory management unit includes logic to, based upon a flush-on-fail (FoF) mode, skip execution of the flush-on-commit instruction and to flush the dirty data from the volatile cache upon a subsequent FoF operation.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: January 30, 2018
    Assignee: Intel Corporation
    Inventors: Sanjay K. Kumar, Rajesh M. Sankaran, Subramanya R. Dulloor, Andrew V. Anderson
  • Publication number: 20170357584
    Abstract: A processor includes a memory management unit and a front end including a decoder. The decoder includes logic to receive a flush-on-commit (FoC) instruction to flush dirty data from a volatile cache to a persistent memory upon commitment of a store associated with the FoC instruction. The memory management unit includes logic to, based upon a flush-on-fail (FoF) mode, skip execution of the flush-on-commit instruction and to flush the dirty data from the volatile cache upon a subsequent FoF operation.
    Type: Application
    Filed: August 28, 2017
    Publication date: December 14, 2017
    Applicant: Intel Corporation
    Inventors: Sanjay K. KUMAR, Rajesh M. Sankaran, Subramanya R. Dulloor, Andrew V. Anderson