Abstract: An on-die temperature sensor measures temperature during a temperature-measurement session. A PTAT (proportional-to-absolute-temperature) generator generates an analog PTAT voltage that is dependent on temperature. A ramp generator generates a changing, analog ramp voltage whose rate of change is dependent on the PTAT voltage, such that the rate of change of the ramp voltage is dependent on the temperature. A comparator compares the ramp voltage to a reference voltage to detect termination of the temperature-measurement session. A counter generates a count value based on the duration of the temperature-measurement session, where the count value is mapped to the measured temperature using a lookup table. The PTAT generator has (i) two npn-type bipolar devices that generate a base-to-emitter voltage difference that is dependent on temperature and function as an amplifier input stage and (ii) circuitry to generate base currents for the bipolar devices to avoid current loading at the PTAT output.

Abstract: An on-die temperature sensor measures temperature during a temperature-measurement session. A PTAT (proportional-to-absolute-temperature) generator generates an analog PTAT voltage that is dependent on temperature. A ramp generator generates a changing, analog ramp voltage whose rate of change is dependent on the PTAT voltage, such that the rate of change of the ramp voltage is dependent on the temperature. A comparator compares the ramp voltage to a reference voltage to detect termination of the temperature-measurement session. A counter generates a count value based on the duration of the temperature-measurement session, where the count value is mapped to the measured temperature using a lookup table. The PTAT generator has (i) two npn-type bipolar devices that generate a base-to-emitter voltage difference that is dependent on temperature and function as an amplifier input stage and (ii) circuitry to generate base currents for the bipolar devices to avoid current loading at the PTAT output.

Abstract: A power-on-reset (POR) circuit for a system-on-chip (SOC) includes a biased switching element having a source, drain, and gate, with the source being connected to a supply voltage and the drain and gate being connected to a control line. The POR circuit further includes a first delay switching element having a source connected to a reduced supply voltage, a gate connected to the control line, and a drain, and an inverter having an input and an output, with the input being connected to the drain of the first delay switching element. The inverter includes a first CMOS inverter coupled between the supply voltage and a reference voltage. A first capacitor is coupled between the inverter input and the reference voltage. A second capacitor coupled between the inverter input and an output of the first CMOS inverter.

Abstract: A charge pump includes a charge pump core circuit, a replica bias circuit, and a differential amplifier. The charge pump core circuit includes current source and sink circuits for charging and discharging an output node of the charge pump core circuit. The current source and current sink circuits are user programmable using bit signals to adjust a bandwidth and a phase margin of a phase-locked loop (PLL) that includes the charge pump. An impedance of the replica bias circuit varies based on the bit signals. The differential amplifier and the replica bias circuit form a feedback loop that reduces current mismatch between the current source and sink circuits.

Abstract: A level shifter that shifts a voltage level of an input signal, where the input signal oscillates between a voltage level of a first supply voltage and ground. The level shifter includes a bias circuit, and first and second transistors. The bias circuit provides a bias voltage to the first transistor based on the first supply voltage. The second transistor is connected in series with the first transistor, and the series combination is connected between voltage supplies that provide second and third supply voltages. The second transistor receives the input signal at its gate, and a level-shifted version of the input signal is output at a node between the first and second transistors. The level-shifted signal oscillates between the voltage levels of the second and third supply voltages.

Abstract: A phase-locked loop (PLL) for generating an oscillating signal includes a frequency bounding circuit. When a frequency of the oscillating signal is greater than a first threshold value, which is greater than a maximum normal operational frequency of the PLL, the frequency bounding circuit forces a charge pump to discharge a loop filter until the oscillating signal frequency is less than a second threshold value that is within the normal operational frequency range of the PLL. When the frequency of the oscillating signal is less than a third threshold value, which is less than a minimum normal operational frequency of the PLL, the frequency bounding circuit forces the charge pump to charge the loop filter until the oscillating signal frequency is greater than a fourth threshold value that is within the normal operational frequency range of the PLL.

Abstract: A level shifter operates using first and second input signals. When the first and second input signals are in respective first and second states, a first switching element is activated and an output node is pulled toward a first voltage, first pull-down protection and first pull-down switching elements are deactivated, a first protection node is connected to a first bias voltage, second pull-down protection and second pull-down switching elements are activated, and a second protection node is pulled to a second voltage. When the first and second input signals are in respective second and first states, the first switching element is deactivated, the first pull-down protection and first pull-down switching elements are activated, the output node and the first protection node are pulled toward the second voltage, the second pull-down protection and second pull-down switching elements are deactivated, and the second protection node is connected to the first bias voltage.

Abstract: A low-voltage, self-biased, high-speed comparator receives and compares an analog input signal to a reference signal and generates a binary output signal whose value indicates whether the input signal is greater than or less than the reference signal. The comparator includes a current mirror, a voltage divider for establishing a midpoint voltage for generating a current reference for the current mirror, and a compensation circuit for stabilizing the comparator by preventing oscillations.

Abstract: A capacitor charging circuit has input, output and control nodes, first and second series connected primary FETs, and first and second leakage current reduction FETs. All of the FETs have their gates coupled to the control node. The first primary FET is coupled between the input and output nodes, and the second primary FET is coupled between the output node and a leakage current reduction node. The first leakage current reduction FET is coupled between a supply line and the leakage current reduction node, and the second leakage current reduction FET is coupled between the leakage current reduction node and ground. When a control signal at the control node is low, the first primary FET and the first leakage current reduction FET are conductive, and the second primary FET and the second leakage current reduction FET are non-conductive, which eliminates sub-threshold leakage current flowing through the second primary FET.

Abstract: A bandgap voltage reference and voltage regulator system includes a bandgap voltage reference circuit and a voltage regulator circuit that share a single, common amplifier. The amplifier acts as a gain stage for the reference circuit and as an error amplifier for a driver stage of the regulator circuit. The regulator circuit has an input reference generated by the reference circuit, and the reference circuit acts as a load to the driver stage, obviating the need for a bias resistance network. By sharing the amplifier and obviating the need for a resistance network, the area and overall quiescent current of the system are reduced. The system can be implemented in CMOS/BiCMOS technology and is suited for low power applications.

Abstract: Systems and methods for low-power voltage tamper detection are described. In some embodiments, an integrated circuit may include source-follower circuitry configured to produce a scaled down supply voltage. The integrated circuit may also include undervoltage detection circuitry coupled to the source-follower circuitry, the undervoltage detection circuitry configured to output a first signal having a first logic value if the scaled down supply voltage is greater than a low threshold voltage or a second logic value if the scaled down supply voltage is smaller than the low threshold voltage. Additionally or alternatively, the integrated circuit may include overvoltage detection circuitry coupled to the source-follower circuitry, the overvoltage detection circuitry configured to output a second signal having the first logic value if the scaled down supply voltage is smaller than a high threshold voltage or the second logic value if the scaled down supply voltage is greater than the high threshold voltage.

Abstract: A relaxation oscillator for generating an output clock signal includes an RC circuit, a self-biased comparator stage, and a logic circuit. The RC circuit generates first and second comparator input signals that are provided to the self-biased comparator stage. The self-biased comparator stage includes first and second input stages and a voltage reference circuit. Each of the first and second input stages in conjunction with the voltage reference circuit forms a comparator, i.e., first and second comparators corresponding to the first and second input stages, respectively. The self-biased comparator stage generates first and second comparator output signals, based on the first and second comparator input signals. The first and second comparator output signals are provided to the logic circuit that generates the output clock signal.

Abstract: A relaxation oscillator for generating an output clock signal includes an RC circuit, a self-biased comparator stage, and a logic circuit. The RC circuit generates first and second comparator input signals that are provided to the self-biased comparator stage. The self-biased comparator stage includes first and second input stages and a voltage reference circuit. Each of the first and second input stages in conjunction with the voltage reference circuit forms a comparator, i.e., first and second comparators corresponding to the first and second input stages, respectively. The self-biased comparator stage generates first and second comparator output signals, based on the first and second comparator input signals. The first and second comparator output signals are provided to the logic circuit that generates the output clock signal.

Abstract: A capacitor charging circuit has input, output and control nodes, first and second series connected primary FETs, and first and second leakage current reduction FETs. All of the FETs have their gates coupled to the control node. The first primary FET is coupled between the input and output nodes, and the second primary FET is coupled between the output node and a leakage current reduction node. The first leakage current reduction FET is coupled between a supply line and the leakage current reduction node, and the second leakage current reduction FET is coupled between the leakage current reduction node and ground. When a control signal at the control node is low, the first primary FET and the first leakage current reduction FET are conductive, and the second primary FET and the second leakage current reduction FET are non-conductive, which eliminates sub-threshold leakage current flowing through the second primary FET.

Abstract: A relaxation oscillator for generating an output clock signal includes a RC circuit, a bias generation stage, first and second comparator stages, and a logic circuit. The RC circuit generates first and second comparator input signals that are transmitted to the first and second comparator stages. The bias generation stage generates first and second bias voltages that are provided to each of the first and second comparator stages. The first and second comparator stages generate first and second comparator output signals, respectively, based on the first and second comparator input signals and the first and second bias voltages. The first and second comparator output signals are provided to the logic circuit that generates the output clock signal.

Abstract: Systems and methods for low-power voltage tamper detection are described. In some embodiments, an integrated circuit may include source-follower circuitry configured to produce a scaled down supply voltage. The integrated circuit may also include undervoltage detection circuitry coupled to the source-follower circuitry, the undervoltage detection circuitry configured to output a first signal having a first logic value if the scaled down supply voltage is greater than a low threshold voltage or a second logic value if the scaled down supply voltage is smaller than the low threshold voltage. Additionally or alternatively, the integrated circuit may include overvoltage detection circuitry coupled to the source-follower circuitry, the overvoltage detection circuitry configured to output a second signal having the first logic value if the scaled down supply voltage is smaller than a high threshold voltage or the second logic value if the scaled down supply voltage is greater than the high threshold voltage.

Abstract: A relaxation oscillator for generating an output clock signal includes a RC circuit, a bias generation stage, first and second comparator stages, and a logic circuit. The RC circuit generates first and second comparator input signals that are transmitted to the first and second comparator stages. The bias generation stage generates first and second bias voltages that are provided to each of the first and second comparator stages. The first and second comparator stages generate first and second comparator output signals, respectively, based on the first and second comparator input signals and the first and second bias voltages. The first and second comparator output signals are provided to the logic circuit that generates the output clock signal.

Abstract: A bandgap voltage reference and voltage regulator system includes a bandgap voltage reference circuit and a voltage regulator circuit that share a single, common amplifier. The amplifier acts as a gain stage for the reference circuit and as an error amplifier for a driver stage of the regulator circuit. The regulator circuit has an input reference generated by the reference circuit, and the reference circuit acts as a load to the driver stage, obviating the need for a bias resistance network. By sharing the amplifier and obviating the need for a resistance network, the area and overall quiescent current of the system are reduced. The system can be implemented in CMOS/BiCMOS technology and is suited for low power applications.

Abstract: A phase to digital converter for a digital PLL (Phase Locked Loop) provides an output in the same or single reference clock period for which it is digitizing the phase error information. The phase to digital converter operates on a positive edge of the reference clock and a digital filter operates on the negative edge of the reference clock so the phase correction performed by the PLL occurs in the same reference clock cycle in which the phase to digital converter is digitizing the phase error information.

Abstract: A dual loop PLL for generating an oscillator signal initially operates in a digital loop to achieve a frequency lock between an input reference signal and a feedback signal and then the PLL operates in an analog loop to achieve a phase lock. After attaining the phase lock, the analog loop is used to maintain the phase lock across frequency and phase variation due to changes in temperature and supply.