Patents by Inventor Sanjay Kamath
Sanjay Kamath has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12209120Abstract: The present disclosure provides activatable binding polypeptides (ABPs), which contain a target binding moiety (TBM), a masking moiety (MM), and a cleavable moiety (CM). The present disclosure provides activatable antibody compositions, which contain a TBM containing an antigen binding domain (ABD), a MM and a CM. Furthermore the present disclosure also provides ABPs which contain a first TBM, a second TBM and a CM. The ABPs exhibit an “activatable” conformation such that at least one of the TBMs is less accessible to target when uncleaved than after cleavage of the CM in the presence of a cleaving agent capable of cleaving the CM. The disclosure further provides libraries of candidate ABPs, methods of screening to identify such ABPs, and methods of use. The disclosure further provides ABPs having TBMs that bind VEGF, CTLA-4, or VCAM, ABPs having a first TBM that binds VEGF and a second TBM that binds FGF, as well as compositions and methods of use.Type: GrantFiled: April 30, 2021Date of Patent: January 28, 2025Assignees: The Regents of the University of California, CytomX Therapeutics, Inc.Inventors: Patrick Sean Daugherty, Nancy Stagliano, Jerry Thomas, Kathryn Kamath, James W. West, Sanjay Khare, Jason Sagert
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Publication number: 20240304437Abstract: Capacitor devices containing silicon boron nitride with high boron concentration are provided. In one or more examples, a capacitor device is provided and contains a stopper layer containing silicon boron nitride and disposed on a substrate, a dielectric layer disposed on the stopper layer, vias formed within the dielectric layer and the stopper layer, metal contacts disposed on bottoms of the vias, a nitride barrier layer containing a metal nitride material and disposed on walls of the vias and disposed on the metal contacts, and an oxide layer disposed within the vias on the nitride barrier layer, wherein the oxide layer contains one or more holes or voids formed therein. The silicon boron nitride contains about 18 atomic percent (at %) to about 50 at % of boron.Type: ApplicationFiled: April 29, 2024Publication date: September 12, 2024Inventors: Chuanxi YANG, Hang YU, Sanjay KAMATH, Deenesh PADHI, Honggun KIM, Euhngi LEE, Zubin HUANG, Diwakar N. KEDLAYA, Rui CHENG, Karthik JANAKIRAMAN
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Patent number: 12040210Abstract: Exemplary semiconductor processing systems include a processing chamber, a power supply, and a chuck disposed at least partially within the processing chamber. The chuck includes a chuck body defining a vacuum port. The chuck also includes first and second coplanar electrodes embedded in the chuck body and connected to the power supply. In some examples, coplanar electrodes include concentric electrodes defining a concentric gap in between. Exemplary semiconductor processing methods may include activating the power supply for the electrostatic chuck to secure a semiconductor substrate on the body of the chuck and/or activating the vacuum port defined by the body of the electrostatic chuck. Some processing can be carried out at increased pressure, while other processing can be carried out at reduced pressure with increased chucking voltage.Type: GrantFiled: October 19, 2020Date of Patent: July 16, 2024Assignee: Applied Materials, Inc.Inventors: Jian Li, Dmitry A. Dzilno, Juan Carlos Rocha-Alvarez, Paul L. Brillhart, Akshay Gunaji, Mayur Govind Kulkarni, Sandeep Bindgi, Sanjay Kamath, Kwangduk Douglas Lee, Zongbin Wang, Yubin Zhang, Yong Xiang Lim
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Patent number: 11817313Abstract: Exemplary deposition methods may include forming a plasma of a silicon-containing precursor and at least one additional precursor within a processing region of a semiconductor processing chamber. The processing region may house a semiconductor substrate on a substrate support. The methods may include depositing material on the semiconductor substrate to a target thickness. The methods may include halting delivery of the silicon-containing precursor while maintaining the plasma with the one or more precursors. The methods may include purging the processing region of the semiconductor processing chamber.Type: GrantFiled: February 5, 2020Date of Patent: November 14, 2023Assignee: Applied Materials, Inc.Inventors: Madhu Santosh Kumar Mutyala, Sanjay Kamath, Deenesh Padhi
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Patent number: 11817320Abstract: Implementations described herein generally relate to a method for forming a metal layer and to a method for forming an oxide layer on the metal layer. In one implementation, the metal layer is formed on a seed layer, and the seed layer helps the metal in the metal layer nucleate with small grain size without affecting the conductivity of the metal layer. The metal layer may be formed using plasma enhanced chemical vapor deposition (PECVD) and nitrogen gas may be flowed into the processing chamber along with the precursor gases. In another implementation, a barrier layer is formed on the metal layer in order to prevent the metal layer from being oxidized during subsequent oxide layer deposition process. In another implementation, the metal layer is treated prior to the deposition of the oxide layer in order to prevent the metal layer from being oxidized.Type: GrantFiled: August 29, 2019Date of Patent: November 14, 2023Assignee: Applied Materials, Inc.Inventors: Susmit Singha Roy, Kelvin Chan, Hien Minh Le, Sanjay Kamath, Abhijit Basu Mallick, Srinivas Gandikota, Karthik Janakiraman
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Patent number: 11430654Abstract: Exemplary deposition methods may include forming a plasma of an oxygen-containing precursor within a processing region of a semiconductor processing chamber. The processing region may house a semiconductor substrate on a substrate support. The methods may include, while maintaining the plasma of the oxygen-containing precursor, flowing a silicon-containing precursor into the processing region of the semiconductor processing chamber at a first flow rate. The methods may include ramping the first flow rate of the silicon-containing precursor over a period of time to a second flow rate greater than the first flow rate. The methods may include depositing a silicon-containing material on the semiconductor substrate.Type: GrantFiled: November 27, 2019Date of Patent: August 30, 2022Assignee: Applied Materials, Inc.Inventors: Madhu Santosh Kumar Mutyala, Sanjay Kamath, Deenesh Padhi
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Publication number: 20220119952Abstract: Exemplary deposition methods may include electrostatically chucking a semiconductor substrate at a first voltage within a processing region of a semiconductor processing chamber. The methods may include performing a deposition process. The deposition process may include forming a plasma within the processing region of the semiconductor processing chamber. The methods may include halting formation of the plasma within the semiconductor processing chamber. The methods may include, simultaneously with the halting, increasing the first voltage of electrostatic chucking to a second voltage. The methods may include purging the processing region of the semiconductor processing chamber.Type: ApplicationFiled: October 20, 2020Publication date: April 21, 2022Applicant: Applied Materials, Inc.Inventors: Rana Howlader, Hang Yu, Madhu Santosh Kumar Mutyala, Zheng John Ye, Abhigyan Keshri, Sanjay Kamath, Daemian Raj Benjamin Raj, Deenesh Padhi
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Publication number: 20220122811Abstract: Exemplary deposition methods may include forming a plasma of an oxygen-containing precursor within a processing region of a semiconductor processing chamber. The processing region may house a semiconductor substrate on a substrate support. The methods may include, while maintaining the plasma of the oxygen-containing precursor, flowing a silicon-containing precursor through a faceplate into the processing region of the semiconductor processing chamber. The faceplate may have an impedance of at least 5.75 deciohm. The methods may include depositing a silicon-containing material on the semiconductor substrate.Type: ApplicationFiled: October 16, 2020Publication date: April 21, 2022Applicant: Applied Materials, Inc.Inventors: Madhu Santosh Kumar Mutyala, Sanjay Kamath, Deenesh Padhi, Mayur Govind Kulkarni, Arun Thottappayil
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Publication number: 20220122873Abstract: Exemplary semiconductor processing systems include a processing chamber, a power supply, and a chuck disposed at least partially within the processing chamber. The chuck includes a chuck body defining a vacuum port. The chuck also includes first and second coplanar electrodes embedded in the chuck body and connected to the power supply. In some examples, coplanar electrodes include concentric electrodes defining a concentric gap in between. Exemplary semiconductor processing methods may include activating the power supply for the electrostatic chuck to secure a semiconductor substrate on the body of the chuck and/or activating the vacuum port defined by the body of the electrostatic chuck. Some processing can be carried out at increased pressure, while other processing can be carried out at reduced pressure with increased chucking voltage.Type: ApplicationFiled: October 19, 2020Publication date: April 21, 2022Applicant: Applied Materials, Inc.Inventors: Jian Li, Dmitry A. Dzilno, Juan Carlos Rocha-Alvarez, Paul L. Brillhart, Akshay Gunaji, Mayur Govind Kulkarni, Sandeep Bindgi, Sanjay Kamath, Kwangduk Douglas Lee, Zongbin Wang, Yubin Zhang, Yong Xiang Lim
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Patent number: 11270903Abstract: Exemplary semiconductor processing chambers may include a pedestal comprising a platen configured to support a semiconductor substrate across a surface of the platen. The chambers may include a first conductive mesh incorporated within the platen and configured to operate as a first chucking mesh. The first conductive mesh may extend radially across the platen. The chambers may include a second conductive mesh incorporated within the platen and configured to operate as a second chucking mesh. The second conductive mesh may be characterized by an annular shape. The second conductive mesh may be disposed between the first conductive mesh and the surface of the platen.Type: GrantFiled: December 17, 2019Date of Patent: March 8, 2022Assignee: Applied Materials, Inc.Inventors: Madhu Santosh Kumar Mutyala, Sanjay Kamath, Deenesh Padhi
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Patent number: 11157661Abstract: A process development visualization tool generates a first visualization of a parameter associated with a manufacturing process, and provides a GUI control element associated with a process variable of the manufacturing process, wherein the GUI control element has a first setting associated with a first value for the process variable. The process development tool receives a user input to adjust the GUI control element from the first setting to a second setting, determines a second value for the process variable based on the second setting, and determines a second set of values for the parameter that are associated with the second value for the process variable. The process development tool then generates a second visualization of the parameter, wherein the second visualization represents the second set of values for the parameter that are associated with the second value for the process variable.Type: GrantFiled: December 16, 2019Date of Patent: October 26, 2021Assignee: Applied Materials, Inc.Inventors: Vinayak Veer Vats, Sidharth Bhatia, Garrett Ho-Yee Sin, Pramod Nambiar, Hang Yu, Sanjay Kamath, Deenesh Padhi, Heng-Cheng Pai
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Publication number: 20210242016Abstract: Exemplary deposition methods may include forming a plasma of a silicon-containing precursor and at least one additional precursor within a processing region of a semiconductor processing chamber. The processing region may house a semiconductor substrate on a substrate support. The methods may include depositing material on the semiconductor substrate to a target thickness. The methods may include halting delivery of the silicon-containing precursor while maintaining the plasma with the one or more precursors. The methods may include purging the processing region of the semiconductor processing chamber.Type: ApplicationFiled: February 5, 2020Publication date: August 5, 2021Applicant: Applied Materials, Inc.Inventors: Madhu Santosh Kumar Mutyala, Sanjay Kamath, Deenesh Padhi
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Publication number: 20210183678Abstract: Exemplary semiconductor processing chambers may include a pedestal comprising a platen configured to support a semiconductor substrate across a surface of the platen. The chambers may include a first conductive mesh incorporated within the platen and configured to operate as a first chucking mesh. The first conductive mesh may extend radially across the platen. The chambers may include a second conductive mesh incorporated within the platen and configured to operate as a second chucking mesh. The second conductive mesh may be characterized by an annular shape. The second conductive mesh may be disposed between the first conductive mesh and the surface of the platen.Type: ApplicationFiled: December 17, 2019Publication date: June 17, 2021Applicant: Applied Materials, Inc.Inventors: Madhu Santosh Kumar Mutyala, Sanjay Kamath, Deenesh Padhi
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Publication number: 20210159073Abstract: Exemplary deposition methods may include forming a plasma of an oxygen-containing precursor within a processing region of a semiconductor processing chamber. The processing region may house a semiconductor substrate on a substrate support. The methods may include, while maintaining the plasma of the oxygen-containing precursor, flowing a silicon-containing precursor into the processing region of the semiconductor processing chamber at a first flow rate. The methods may include ramping the first flow rate of the silicon-containing precursor over a period of time to a second flow rate greater than the first flow rate. The methods may include depositing a silicon-containing material on the semiconductor substrate.Type: ApplicationFiled: November 27, 2019Publication date: May 27, 2021Applicant: Applied Materials, Inc.Inventors: Madhu Santosh Kumar Mutyala, Sanjay Kamath, Deenesh Padhi
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Publication number: 20210134592Abstract: Exemplary deposition methods may include delivering a silicon-containing precursor and a carrier precursor to a processing region of a semiconductor processing chamber. The methods may include forming a plasma of the silicon-containing precursor and the carrier precursor within the processing region of the semiconductor processing chamber. The methods may include depositing a first amount of a silicon-containing material on a substrate disposed within the processing region of the semiconductor processing chamber. The depositing may occur at a first chamber pressure. The methods may include adjusting the first chamber pressure to a second chamber pressure less than the first chamber pressure. The methods may include depositing a second amount of the silicon-containing material on the first amount of the silicon-containing material.Type: ApplicationFiled: October 27, 2020Publication date: May 6, 2021Applicant: Applied Materials, inc.Inventors: Madhu Santosh Kumar Mutyala, Sanjay Kamath, Deenesh Padhi
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Publication number: 20210082732Abstract: Exemplary deposition methods may include electrostatically chucking a semiconductor substrate at a first voltage within a processing region of a semiconductor processing chamber. The methods may include performing a deposition process. The deposition process may include forming a plasma within the processing region of the semiconductor processing chamber. The methods may include halting formation of the plasma within the semiconductor processing chamber. The methods may include, simultaneously with the halting, increasing the first voltage of electrostatic chucking to a second voltage. The methods may include purging the processing region of the semiconductor processing chamber.Type: ApplicationFiled: September 8, 2020Publication date: March 18, 2021Applicant: Applied Materials, Inc.Inventors: Madhu Santosh Kumar Mutyala, Sanjay Kamath, Deenesh Padhi
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Publication number: 20200211834Abstract: Methods for forming the silicon boron nitride layer are provided. The method includes positioning a substrate on a pedestal in a process region within a process chamber, heating a pedestal retaining the substrate, and introducing a first flow of a first process gas and a second flow of a second process gas to the process region. The first flow of the first process gas contains silane, ammonia, helium, nitrogen, argon, and hydrogen. The second flow of the second process gas contains diborane and hydrogen. The method also includes forming a plasma concurrently with the first flow of the first process gas and the second flow of the second process gas to the process region and exposing the substrate to the first process gas, the second process gas, and the plasma to deposit the silicon boron nitride layer on the substrate.Type: ApplicationFiled: December 23, 2019Publication date: July 2, 2020Inventors: Chuanxi YANG, Hang YU, Sanjay KAMATH, Deenesh PADHI, Honggun KIM, Euhngi LEE, Zubin HUANG, Diwakar N. KEDLAYA, Rui CHENG, Karthik JANAKIRAMAN
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Publication number: 20200202044Abstract: A process development visualization tool generates a first visualization of a parameter associated with a manufacturing process, and provides a GUI control element associated with a process variable of the manufacturing process, wherein the GUI control element has a first setting associated with a first value for the process variable. The process development tool receives a user input to adjust the GUI control element from the first setting to a second setting, determines a second value for the process variable based on the second setting, and determines a second set of values for the parameter that are associated with the second value for the process variable. The process development tool then generates a second visualization of the parameter, wherein the second visualization represents the second set of values for the parameter that are associated with the second value for the process variable.Type: ApplicationFiled: December 16, 2019Publication date: June 25, 2020Inventors: Vinayak Veer Vats, Sidharth Bhatia, Garrett Ho-Yee Sin, Pramod Nambiar, Hang Yu, Sanjay Kamath, Deenesh Padhi, Heng-Cheng Pai
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Publication number: 20190393042Abstract: Implementations described herein generally relate to a method for forming a metal layer and to a method for forming an oxide layer on the metal layer. In one implementation, the metal layer is formed on a seed layer, and the seed layer helps the metal in the metal layer nucleate with small grain size without affecting the conductivity of the metal layer. The metal layer may be formed using plasma enhanced chemical vapor deposition (PECVD) and nitrogen gas may be flowed into the processing chamber along with the precursor gases. In another implementation, a barrier layer is formed on the metal layer in order to prevent the metal layer from being oxidized during subsequent oxide layer deposition process. In another implementation, the metal layer is treated prior to the deposition of the oxide layer in order to prevent the metal layer from being oxidized.Type: ApplicationFiled: August 29, 2019Publication date: December 26, 2019Inventors: Susmit SINGHA ROY, Kelvin CHAN, Hien Minh LE, Sanjay KAMATH, Abhijit Basu MALLICK, Srinivas GANDIKOTA, Karthik JANAKIRAMAN
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Patent number: 10410869Abstract: Implementations described herein generally relate to a method for forming a metal layer and to a method for forming an oxide layer on the metal layer. In one implementation, the metal layer is formed on a seed layer, and the seed layer helps the metal in the metal layer nucleate with small grain size without affecting the conductivity of the metal layer. The metal layer may be formed using plasma enhanced chemical vapor deposition (PECVD) and nitrogen gas may be flowed into the processing chamber along with the precursor gases. In another implementation, a barrier layer is formed on the metal layer in order to prevent the metal layer from being oxidized during subsequent oxide layer deposition process. In another implementation, the metal layer is treated prior to the deposition of the oxide layer in order to prevent the metal layer from being oxidized.Type: GrantFiled: June 26, 2017Date of Patent: September 10, 2019Assignee: APPLIED MATERIALS, INC.Inventors: Susmit Singha Roy, Kelvin Chan, Hien Minh Le, Sanjay Kamath, Abhijit Basu Mallick, Srinivas Gandikota, Karthik Janakiraman