Patents by Inventor Sanjay Kamath

Sanjay Kamath has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11817313
    Abstract: Exemplary deposition methods may include forming a plasma of a silicon-containing precursor and at least one additional precursor within a processing region of a semiconductor processing chamber. The processing region may house a semiconductor substrate on a substrate support. The methods may include depositing material on the semiconductor substrate to a target thickness. The methods may include halting delivery of the silicon-containing precursor while maintaining the plasma with the one or more precursors. The methods may include purging the processing region of the semiconductor processing chamber.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: November 14, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Madhu Santosh Kumar Mutyala, Sanjay Kamath, Deenesh Padhi
  • Patent number: 11817320
    Abstract: Implementations described herein generally relate to a method for forming a metal layer and to a method for forming an oxide layer on the metal layer. In one implementation, the metal layer is formed on a seed layer, and the seed layer helps the metal in the metal layer nucleate with small grain size without affecting the conductivity of the metal layer. The metal layer may be formed using plasma enhanced chemical vapor deposition (PECVD) and nitrogen gas may be flowed into the processing chamber along with the precursor gases. In another implementation, a barrier layer is formed on the metal layer in order to prevent the metal layer from being oxidized during subsequent oxide layer deposition process. In another implementation, the metal layer is treated prior to the deposition of the oxide layer in order to prevent the metal layer from being oxidized.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: November 14, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Susmit Singha Roy, Kelvin Chan, Hien Minh Le, Sanjay Kamath, Abhijit Basu Mallick, Srinivas Gandikota, Karthik Janakiraman
  • Patent number: 11430654
    Abstract: Exemplary deposition methods may include forming a plasma of an oxygen-containing precursor within a processing region of a semiconductor processing chamber. The processing region may house a semiconductor substrate on a substrate support. The methods may include, while maintaining the plasma of the oxygen-containing precursor, flowing a silicon-containing precursor into the processing region of the semiconductor processing chamber at a first flow rate. The methods may include ramping the first flow rate of the silicon-containing precursor over a period of time to a second flow rate greater than the first flow rate. The methods may include depositing a silicon-containing material on the semiconductor substrate.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: August 30, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Madhu Santosh Kumar Mutyala, Sanjay Kamath, Deenesh Padhi
  • Publication number: 20220122873
    Abstract: Exemplary semiconductor processing systems include a processing chamber, a power supply, and a chuck disposed at least partially within the processing chamber. The chuck includes a chuck body defining a vacuum port. The chuck also includes first and second coplanar electrodes embedded in the chuck body and connected to the power supply. In some examples, coplanar electrodes include concentric electrodes defining a concentric gap in between. Exemplary semiconductor processing methods may include activating the power supply for the electrostatic chuck to secure a semiconductor substrate on the body of the chuck and/or activating the vacuum port defined by the body of the electrostatic chuck. Some processing can be carried out at increased pressure, while other processing can be carried out at reduced pressure with increased chucking voltage.
    Type: Application
    Filed: October 19, 2020
    Publication date: April 21, 2022
    Applicant: Applied Materials, Inc.
    Inventors: Jian Li, Dmitry A. Dzilno, Juan Carlos Rocha-Alvarez, Paul L. Brillhart, Akshay Gunaji, Mayur Govind Kulkarni, Sandeep Bindgi, Sanjay Kamath, Kwangduk Douglas Lee, Zongbin Wang, Yubin Zhang, Yong Xiang Lim
  • Publication number: 20220122811
    Abstract: Exemplary deposition methods may include forming a plasma of an oxygen-containing precursor within a processing region of a semiconductor processing chamber. The processing region may house a semiconductor substrate on a substrate support. The methods may include, while maintaining the plasma of the oxygen-containing precursor, flowing a silicon-containing precursor through a faceplate into the processing region of the semiconductor processing chamber. The faceplate may have an impedance of at least 5.75 deciohm. The methods may include depositing a silicon-containing material on the semiconductor substrate.
    Type: Application
    Filed: October 16, 2020
    Publication date: April 21, 2022
    Applicant: Applied Materials, Inc.
    Inventors: Madhu Santosh Kumar Mutyala, Sanjay Kamath, Deenesh Padhi, Mayur Govind Kulkarni, Arun Thottappayil
  • Publication number: 20220119952
    Abstract: Exemplary deposition methods may include electrostatically chucking a semiconductor substrate at a first voltage within a processing region of a semiconductor processing chamber. The methods may include performing a deposition process. The deposition process may include forming a plasma within the processing region of the semiconductor processing chamber. The methods may include halting formation of the plasma within the semiconductor processing chamber. The methods may include, simultaneously with the halting, increasing the first voltage of electrostatic chucking to a second voltage. The methods may include purging the processing region of the semiconductor processing chamber.
    Type: Application
    Filed: October 20, 2020
    Publication date: April 21, 2022
    Applicant: Applied Materials, Inc.
    Inventors: Rana Howlader, Hang Yu, Madhu Santosh Kumar Mutyala, Zheng John Ye, Abhigyan Keshri, Sanjay Kamath, Daemian Raj Benjamin Raj, Deenesh Padhi
  • Patent number: 11270903
    Abstract: Exemplary semiconductor processing chambers may include a pedestal comprising a platen configured to support a semiconductor substrate across a surface of the platen. The chambers may include a first conductive mesh incorporated within the platen and configured to operate as a first chucking mesh. The first conductive mesh may extend radially across the platen. The chambers may include a second conductive mesh incorporated within the platen and configured to operate as a second chucking mesh. The second conductive mesh may be characterized by an annular shape. The second conductive mesh may be disposed between the first conductive mesh and the surface of the platen.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: March 8, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Madhu Santosh Kumar Mutyala, Sanjay Kamath, Deenesh Padhi
  • Patent number: 11157661
    Abstract: A process development visualization tool generates a first visualization of a parameter associated with a manufacturing process, and provides a GUI control element associated with a process variable of the manufacturing process, wherein the GUI control element has a first setting associated with a first value for the process variable. The process development tool receives a user input to adjust the GUI control element from the first setting to a second setting, determines a second value for the process variable based on the second setting, and determines a second set of values for the parameter that are associated with the second value for the process variable. The process development tool then generates a second visualization of the parameter, wherein the second visualization represents the second set of values for the parameter that are associated with the second value for the process variable.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: October 26, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Vinayak Veer Vats, Sidharth Bhatia, Garrett Ho-Yee Sin, Pramod Nambiar, Hang Yu, Sanjay Kamath, Deenesh Padhi, Heng-Cheng Pai
  • Publication number: 20210242016
    Abstract: Exemplary deposition methods may include forming a plasma of a silicon-containing precursor and at least one additional precursor within a processing region of a semiconductor processing chamber. The processing region may house a semiconductor substrate on a substrate support. The methods may include depositing material on the semiconductor substrate to a target thickness. The methods may include halting delivery of the silicon-containing precursor while maintaining the plasma with the one or more precursors. The methods may include purging the processing region of the semiconductor processing chamber.
    Type: Application
    Filed: February 5, 2020
    Publication date: August 5, 2021
    Applicant: Applied Materials, Inc.
    Inventors: Madhu Santosh Kumar Mutyala, Sanjay Kamath, Deenesh Padhi
  • Publication number: 20210183678
    Abstract: Exemplary semiconductor processing chambers may include a pedestal comprising a platen configured to support a semiconductor substrate across a surface of the platen. The chambers may include a first conductive mesh incorporated within the platen and configured to operate as a first chucking mesh. The first conductive mesh may extend radially across the platen. The chambers may include a second conductive mesh incorporated within the platen and configured to operate as a second chucking mesh. The second conductive mesh may be characterized by an annular shape. The second conductive mesh may be disposed between the first conductive mesh and the surface of the platen.
    Type: Application
    Filed: December 17, 2019
    Publication date: June 17, 2021
    Applicant: Applied Materials, Inc.
    Inventors: Madhu Santosh Kumar Mutyala, Sanjay Kamath, Deenesh Padhi
  • Publication number: 20210159073
    Abstract: Exemplary deposition methods may include forming a plasma of an oxygen-containing precursor within a processing region of a semiconductor processing chamber. The processing region may house a semiconductor substrate on a substrate support. The methods may include, while maintaining the plasma of the oxygen-containing precursor, flowing a silicon-containing precursor into the processing region of the semiconductor processing chamber at a first flow rate. The methods may include ramping the first flow rate of the silicon-containing precursor over a period of time to a second flow rate greater than the first flow rate. The methods may include depositing a silicon-containing material on the semiconductor substrate.
    Type: Application
    Filed: November 27, 2019
    Publication date: May 27, 2021
    Applicant: Applied Materials, Inc.
    Inventors: Madhu Santosh Kumar Mutyala, Sanjay Kamath, Deenesh Padhi
  • Publication number: 20210134592
    Abstract: Exemplary deposition methods may include delivering a silicon-containing precursor and a carrier precursor to a processing region of a semiconductor processing chamber. The methods may include forming a plasma of the silicon-containing precursor and the carrier precursor within the processing region of the semiconductor processing chamber. The methods may include depositing a first amount of a silicon-containing material on a substrate disposed within the processing region of the semiconductor processing chamber. The depositing may occur at a first chamber pressure. The methods may include adjusting the first chamber pressure to a second chamber pressure less than the first chamber pressure. The methods may include depositing a second amount of the silicon-containing material on the first amount of the silicon-containing material.
    Type: Application
    Filed: October 27, 2020
    Publication date: May 6, 2021
    Applicant: Applied Materials, inc.
    Inventors: Madhu Santosh Kumar Mutyala, Sanjay Kamath, Deenesh Padhi
  • Publication number: 20210082732
    Abstract: Exemplary deposition methods may include electrostatically chucking a semiconductor substrate at a first voltage within a processing region of a semiconductor processing chamber. The methods may include performing a deposition process. The deposition process may include forming a plasma within the processing region of the semiconductor processing chamber. The methods may include halting formation of the plasma within the semiconductor processing chamber. The methods may include, simultaneously with the halting, increasing the first voltage of electrostatic chucking to a second voltage. The methods may include purging the processing region of the semiconductor processing chamber.
    Type: Application
    Filed: September 8, 2020
    Publication date: March 18, 2021
    Applicant: Applied Materials, Inc.
    Inventors: Madhu Santosh Kumar Mutyala, Sanjay Kamath, Deenesh Padhi
  • Publication number: 20200211834
    Abstract: Methods for forming the silicon boron nitride layer are provided. The method includes positioning a substrate on a pedestal in a process region within a process chamber, heating a pedestal retaining the substrate, and introducing a first flow of a first process gas and a second flow of a second process gas to the process region. The first flow of the first process gas contains silane, ammonia, helium, nitrogen, argon, and hydrogen. The second flow of the second process gas contains diborane and hydrogen. The method also includes forming a plasma concurrently with the first flow of the first process gas and the second flow of the second process gas to the process region and exposing the substrate to the first process gas, the second process gas, and the plasma to deposit the silicon boron nitride layer on the substrate.
    Type: Application
    Filed: December 23, 2019
    Publication date: July 2, 2020
    Inventors: Chuanxi YANG, Hang YU, Sanjay KAMATH, Deenesh PADHI, Honggun KIM, Euhngi LEE, Zubin HUANG, Diwakar N. KEDLAYA, Rui CHENG, Karthik JANAKIRAMAN
  • Publication number: 20200202044
    Abstract: A process development visualization tool generates a first visualization of a parameter associated with a manufacturing process, and provides a GUI control element associated with a process variable of the manufacturing process, wherein the GUI control element has a first setting associated with a first value for the process variable. The process development tool receives a user input to adjust the GUI control element from the first setting to a second setting, determines a second value for the process variable based on the second setting, and determines a second set of values for the parameter that are associated with the second value for the process variable. The process development tool then generates a second visualization of the parameter, wherein the second visualization represents the second set of values for the parameter that are associated with the second value for the process variable.
    Type: Application
    Filed: December 16, 2019
    Publication date: June 25, 2020
    Inventors: Vinayak Veer Vats, Sidharth Bhatia, Garrett Ho-Yee Sin, Pramod Nambiar, Hang Yu, Sanjay Kamath, Deenesh Padhi, Heng-Cheng Pai
  • Publication number: 20190393042
    Abstract: Implementations described herein generally relate to a method for forming a metal layer and to a method for forming an oxide layer on the metal layer. In one implementation, the metal layer is formed on a seed layer, and the seed layer helps the metal in the metal layer nucleate with small grain size without affecting the conductivity of the metal layer. The metal layer may be formed using plasma enhanced chemical vapor deposition (PECVD) and nitrogen gas may be flowed into the processing chamber along with the precursor gases. In another implementation, a barrier layer is formed on the metal layer in order to prevent the metal layer from being oxidized during subsequent oxide layer deposition process. In another implementation, the metal layer is treated prior to the deposition of the oxide layer in order to prevent the metal layer from being oxidized.
    Type: Application
    Filed: August 29, 2019
    Publication date: December 26, 2019
    Inventors: Susmit SINGHA ROY, Kelvin CHAN, Hien Minh LE, Sanjay KAMATH, Abhijit Basu MALLICK, Srinivas GANDIKOTA, Karthik JANAKIRAMAN
  • Patent number: 10410869
    Abstract: Implementations described herein generally relate to a method for forming a metal layer and to a method for forming an oxide layer on the metal layer. In one implementation, the metal layer is formed on a seed layer, and the seed layer helps the metal in the metal layer nucleate with small grain size without affecting the conductivity of the metal layer. The metal layer may be formed using plasma enhanced chemical vapor deposition (PECVD) and nitrogen gas may be flowed into the processing chamber along with the precursor gases. In another implementation, a barrier layer is formed on the metal layer in order to prevent the metal layer from being oxidized during subsequent oxide layer deposition process. In another implementation, the metal layer is treated prior to the deposition of the oxide layer in order to prevent the metal layer from being oxidized.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: September 10, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Susmit Singha Roy, Kelvin Chan, Hien Minh Le, Sanjay Kamath, Abhijit Basu Mallick, Srinivas Gandikota, Karthik Janakiraman
  • Publication number: 20180350563
    Abstract: Embodiments of the disclosure generally relate to a method of processing a semiconductor substrate at a temperature less than 250 degrees Celsius. In one embodiment, the method includes loading the substrate with the deposited film into a pressure vessel, exposing the substrate to a processing gas comprising an oxidizer at a pressure greater than about 2 bars, and maintaining the pressure vessel at a temperature between a condensation point of the processing gas and about 250 degrees Celsius.
    Type: Application
    Filed: May 29, 2018
    Publication date: December 6, 2018
    Inventors: Pramit MANNA, Abhijit Basu MALLICK, Kurtis LESCHKIES, Steven VERHAVERBEKE, Sanjay KAMATH, Zongbin WANG, Hanwen ZHANG, Shishi JIANG
  • Publication number: 20170372953
    Abstract: Implementations described herein generally relate to a method for forming a metal layer and to a method for forming an oxide layer on the metal layer. In one implementation, the metal layer is formed on a seed layer, and the seed layer helps the metal in the metal layer nucleate with small grain size without affecting the conductivity of the metal layer. The metal layer may be formed using plasma enhanced chemical vapor deposition (PECVD) and nitrogen gas may be flowed into the processing chamber along with the precursor gases. In another implementation, a barrier layer is formed on the metal layer in order to prevent the metal layer from being oxidized during subsequent oxide layer deposition process. In another implementation, the metal layer is treated prior to the deposition of the oxide layer in order to prevent the metal layer from being oxidized.
    Type: Application
    Filed: June 26, 2017
    Publication date: December 28, 2017
    Inventors: Susmit Singha ROY, Kelvin CHAN, Hien Minh LE, Sanjay KAMATH, Abhijit Basu MALLICK, Srinivas GANDIKOTA, Karthik JANAKIRAMAN
  • Patent number: 9826433
    Abstract: According to a disclosed embodiment, a flow indication counter is incremented each time a data packet is transmitted from a buffer. When the number of data packets transmitted equals or exceeds a threshold number, a flow indication message comprising the buffer window size is generated and transmitted to the base station controller. Further, flow indication messages can be generated and transmitted every threshold time interval, independently of the number of data packets transmitted to ensure that flow indication messages are sent at least every preset time interval. Moreover, a system for flow control can be constructed comprising a flow indication counter module configured to provide an updated number of data packets transmitted. The system further comprises a window size monitoring module which determines the buffer window size and a message generating module which generates a flow indication message comprising the buffer window size.
    Type: Grant
    Filed: May 14, 2007
    Date of Patent: November 21, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Sanjay Kamath, Michael A. Kongelf, Leif Woodahl