Abstract: A powerline communication (PLC) device can be configured to execute functionality for zero cross sampling and detection. When the PLC device is directly coupled to a high-voltage PLC network, the PLC device can comprise printed safety capacitors in series with a high-voltage input AC powerline signal to safely couple the high-voltage AC powerline signal to the low-voltage processing circuit. The PLC device can also comprise an ADC to sample a scaled AC powerline signal and to obtain zero cross information. When the PLC device is part of an embedded PLC application, dynamic loading can affect the integrity of a low voltage zero cross signal that is used to extract zero cross information. After digitizing the zero cross signal, the PLC device can execute functionality to minimize/eliminate voltage drops caused by dynamic loading and obtain the zero cross information.

Abstract: A switched mode, high linearity power amplifier can include a dynamic quantizer, a pulse width modulator and an output driver. In one embodiment, the dynamic quantizer can include a sigma-delta modulator configured to provide a multi-level digital signal. The pulse width modulator can receive the multi-level digital signal and provide a variable pulse width signal based, at least in part, on the multi-level digital signal. The output driver can include a class D output driver. The output driver can receive the variable pulse width signal to operate the class D output driver and provide an amplified signal. In one embodiment, the output driver can adjust the amplified signal to compensate for output errors.

Abstract: A clock modulator can include two configurable delay units and can receive a baseband signal and a clock signal. The two configurable delay units can generate two delayed clock signals, each with different delay amounts. The delay amounts can be based on the baseband signal. The delayed clock signals can be combined to generate a modulated clock signal. A quadrature modulated clock signal can be generated when a first clock modulator receives a first baseband signal and a first clock signal and a second clock modulator receives a second baseband signal and a second clock signal. The first clock signal can be a ninety-degree phase shifted version of the second clock signal. The modulated clock signal from the first clock modulator can be combined with the modulated clock signal from the second clock modulator to generate the quadrature modulated clock signal.

Abstract: A clock modulator can include two configurable delay units and can receive a baseband signal and a clock signal. The two configurable delay units can generate two delayed clock signals, each with different delay amounts. The delay amounts can be based on the baseband signal. The delayed clock signals can be combined to generate a modulated clock signal. A quadrature modulated clock signal can be generated when a first clock modulator receives a first baseband signal and a first clock signal and a second clock modulator receives a second baseband signal and a second clock signal. The first clock signal can be a ninety-degree phase shifted version of the second clock signal. The modulated clock signal from the first clock modulator can be combined with the modulated clock signal from the second clock modulator to generate the quadrature modulated clock signal.

Abstract: A QAM transmitter is disclosed that may reduce the frequency of local clock signals and/or reduce the switching frequency of driver circuits when generating a QAM output signal for transmission. The QAM transmitter may generate a number of PWM signals indicative of in-phase (I) and quadrature (Q) signal components, and then use one or more selected even-order harmonics of the PWM signals to generate the QAM output signal. Odd-order harmonics of the PWM signals may be suppressed by selectively combining the PWM signals, and any remaining unwanted even-order harmonics may be suppressed using filters.

Abstract: A switched mode, high linearity power amplifier can include a dynamic quantizer, a pulse width modulator and an output driver. In one embodiment, the dynamic quantizer can include a sigma-delta modulator configured to provide a multi-level digital signal. The pulse width modulator can receive the multi-level digital signal and provide a variable pulse width signal based, at least in part, on the multi-level digital signal. The output driver can include a class D output driver. The output driver can receive the variable pulse width signal to operate the class D output driver and provide an amplified signal. In one embodiment, the output driver can adjust the amplified signal to compensate for output errors.

Abstract: A QAM transmitter is disclosed that may reduce the frequency of local clock signals and/or reduce the switching frequency of driver circuits when generating a QAM output signal for transmission. The QAM transmitter may generate a number of PWM signals indicative of in-phase (I) and quadrature (Q) signal components, and then use one or more selected even-order harmonics of the PWM signals to generate the QAM output signal. Odd-order harmonics of the PWM signals may be suppressed by selectively combining the PWM signals, and any remaining unwanted even-order harmonics may be suppressed using filters.

Abstract: A powerline communication (PLC) device can be configured to execute functionality for zero cross sampling and detection. When the PLC device is directly coupled to a high-voltage PLC network, the PLC device can comprise printed safety capacitors in series with a high-voltage input AC powerline signal to safely couple the high-voltage AC powerline signal to the low-voltage processing circuit. The PLC device can also comprise an ADC to sample a scaled AC powerline signal and to obtain zero cross information. When the PLC device is part of an embedded PLC application, dynamic loading can affect the integrity of a low voltage zero cross signal that is used to extract zero cross information. After digitizing the zero cross signal, the PLC device can execute functionality to minimize/eliminate voltage drops caused by dynamic loading and obtain the zero cross information.

Abstract: A device and method of high-speed transmission is disclosed. The method includes computing a signal quality of a received signal, the received signal being transmitted with a modulation order required by a default transmission modulation format. The signal quality is compared with a signal quality threshold required of the default transmission modulation format. If the signal quality is below the signal quality threshold, an indication of a level of signal quality failure is provided to a transmitter. The transmitter sets a number of un-coded bits within the transmission signal based upon the level of signal quality failure.

Abstract: A device and method of setting transmit power backoff of a transceiver within a network is disclosed. The method includes estimating a channel loss of a channel of the transceiver, obtaining channel loss information, the channel loss information including estimates of channel loss of other channels of the network, obtaining crosstalk information, the crosstalk information including estimates of crosstalk between the channel and other channels of the network, and setting the power backoff based on the channel loss of the channel, the channel information, and the crosstalk information.

Abstract: The invention includes an apparatus and a method for transmitting sub-protocol data units from a plurality of base transceiver stations to a subscriber unit. The method includes estimating time delays required for transferring the sub-protocol data units between a scheduler unit and each of the base transceiver stations. The method further includes the scheduler unit generating a schedule of time slots and frequency blocks in which the sub-protocol data units are to be transmitted from the base transceiver stations to the subscriber unit. The time delays are used to generate the schedule. The time delays can be used to generate a look ahead schedule that compensates for the timing delays of the sub-protocol data units from the scheduler unit to the base transceiver stations. The sub-protocol data units are wirelessly transmitted from the base transceiver stations to the subscriber unit according to the schedule.

Abstract: Embodiments of an Ethernet transceiver are disclosed. The Ethernet transceiver includes a plurality of digital signal streams, at least one digital signal stream being coupled to another of the digital signal streams. A domain transformer transforms sub-blocks of each of the plurality of the digital signal streams from an original domain into a lower complexity domain. A processor joint processes the transformed sub-blocks of the digital signal streams, each joint processed digital signal stream sub-block is influenced by other digital signal streams sub-blocks. An inverse transformer inverse transforms the joint processed signal streams sub-blocks back to the original domain.

Abstract: A method and apparatus of joint processing a plurality of digital signal streams is disclosed. The method includes transforming a plurality of the digital signal streams from an original domain to a lower complexity processing domain. The transformed plurality of digital signal streams are joint processed, wherein the joint processing includes multiplying samples of the plurality of transformed digital signal streams by a processing matrix. The joint processed signal streams are inverse transformed back to the original domain. Diagonal elements of the processing matrix are adaptively selected to cancel transmission echo signals of the plurality digital signal streams introduced during transmission of the plurality digital signal streams depending upon signal coupling of the plurality of digital signal streams.

Abstract: The invention includes a full duplex transceiver for transmitting and receiving communication signals. The transceiver includes 1 to N sample and hold circuits. Each sample and hold circuit receives a first signal that includes a far-end signal, and in some cases an echo signal, and in some cases alternatively or additionally cross-talk signals. The transceiver additionally includes a plurality of subtraction circuits. Each subtraction circuit receives an output of at least one of the sample and hold circuits. Each subtraction circuit subtracts at least a fraction of a replica signal from at least a fraction of the output of the at least one of the sample and hold circuits. The subtraction circuits generate an output that represent the far-end signal with substantially reduced echo and/or cross-talk interference, and is available for additional receiver processing.

Abstract: A method and apparatus of joint processing a plurality of digital signal streams is disclosed. The method includes transforming a plurality of the digital signal streams from an original domain to a lower complexity processing domain. The transformed plurality of digital signal streams are joint processed, wherein the joint processing includes multiplying samples of the plurality of transformed digital signal streams by a processing matrix. The joint processed signal streams are inverse transformed back to the original domain. Diagonal elements of the processing matrix are adaptively selected to cancel transmission echo signals of the plurality digital signal streams introduced during transmission of the plurality digital signal streams depending upon signal coupling of the plurality of digital signal streams.

Abstract: A device and method of setting transmit power backoff of a transceiver within a network is disclosed. The method includes estimating a channel loss of a channel of the transceiver, obtaining channel loss information, the channel loss information including estimates of channel loss of other channels of the network, obtaining crosstalk information, the crosstalk information including estimates of crosstalk between the channel and other channels of the network, and setting the power backoff based on the channel loss of the channel, the channel information, and the crosstalk information.

Abstract: A transceiver is disclosed. The transceiver includes a plurality of digital signal streams, wherein at least one digital signal stream is coupled to another of the digital signal streams. A transform block transforms a plurality of the digital signal streams from an original domain into a lower complexity processing domain. A processor joint processes the transformed digital signal streams, each joint processed digital signal stream being influenced by other digital signal streams. An inverse transform block inverse transforms the joint processed signal streams back to the original domain. A method of joint processing a plurality of digital signal streams is also disclosed. A first act of the method includes transforming a plurality of the digital signal streams from an original domain into a lower complexity processing domain.

Abstract: A device and method of high-speed transmission is disclosed. The method includes computing a signal quality of a received signal, the received signal being transmitted with a modulation order required by a default transmission modulation format. The signal quality is compared with a signal quality threshold required of the default transmission modulation format. If the signal quality is below the signal quality threshold, an indication of a level of signal quality failure is provided to a transmitter. The transmitter sets a number of un-coded bits within the transmission signal based upon the level of signal quality failure.

Abstract: Embodiments of a parallel feedback processor are disclosed. The parallel feedback processor includes a plurality of parallel coupled feedback filters. Each feedback filter includes a non-linear operator. At least one of feedback filter includes a plurality of sub-filters. Each sub-filter computes a one of possible non-linear operator filter outputs of the at least one feedback filter. One sub-filter output is selected as an output of the at least one feedback filter.

Abstract: The present invention includes a wireless communication system. The wireless communication system includes a plurality of transceiver antennae. Each transceiver is spatially separate from at least one other transceiver antenna. Each transceiver antenna includes a transceiver antenna polarization. At least one transceiver antenna has a polarization that is different than at least one other transceiver antenna. Each transceiver antenna transmits a corresponding data stream. The wireless communication system further includes a plurality of receiver antennae. The receiver antennae receive at least one data stream. The transceiver antenna polarization of each transceiver antenna is pre-set to optimize separability of the received data streams. A transmission channel between the transceiver antennae and the receiver antennae can be estimated with a channel matrix. The pre-set transceiver antenna polarization of each transceiver antenna can be determined by minimizing a singular value spread of the channel matrix.