Abstract: A temperature sensor includes a sensing element and a load. Multiple different currents pass through the sensing element in a sequential manner. Based on each current that passes through the sensing element, the sensing element outputs a complementary-to-absolute-temperature (CTAT) voltage and another current. Further, the currents that pass through the sensing element and the currents that the sensing element output separately pass through the load and result in the generation of multiple load voltages across the load. A current density ratio of the temperature sensor is determined based on the load voltages generated across the load. Further, a temperature value indicative of a temperature sensed by the temperature sensor is generated based on the current density ratio and the CTAT voltages outputted by the sensing element based on the different currents that pass therethrough.

Abstract: An integrated circuit (IC) includes one or more active transistors and multiple series-coupled dummy transistors. The dummy transistors are coupled between two active transistors and/or at the ends of each active transistor. When the dummy transistors are coupled between two active transistors, apart from two conductive regions that are coupled to two active transistors, each remaining conductive region of the dummy transistors is maintained in a floating state to control a leakage current between the two active transistors. Similarly, when the dummy transistors are coupled at an end of one active transistor, apart from one conductive region that is coupled to the active transistor, each remaining conductive region of the dummy transistors is maintained in the floating state to control a leakage current between the active transistor and the dummy transistors.

Abstract: A temperature sensor includes a sensing element and a load. Multiple different currents pass through the sensing element in a sequential manner. Based on each current that passes through the sensing element, the sensing element outputs a complementary-to-absolute-temperature (CTAT) voltage and another current. Further, the currents that pass through the sensing element and the currents that the sensing element output separately pass through the load and result in the generation of multiple load voltages across the load. A current density ratio of the temperature sensor is determined based on the load voltages generated across the load. Further, a temperature value indicative of a temperature sensed by the temperature sensor is generated based on the current density ratio and the CTAT voltages outputted by the sensing element based on the different currents that pass therethrough.

Abstract: A clock generator includes an input coupled to receive an input clock signal from a first clock source, and a noise rejection circuit configured to provide an output clock signal based on the input clock signal. The noise rejection circuit includes an event generator having a digital counter circuit. The event generator is configured to generate a first event signal based on a count value of the digital counter circuit, in which the noise rejection circuit is configured to produce an edge on the output clock signal in response to both the event signal and a state of the input clock signal.

Abstract: A level shifter includes a control circuit and a bias circuit. The control circuit receives a bias voltage, a first signal associated with a first voltage domain, and supply voltages associated with a second voltage domain, and outputs a second signal that is associated with the second voltage domain. The bias circuit generates the bias voltage that is indicative of the duty cycle of the second signal, and provides the bias voltage to the control circuit to control the duty cycle of the second signal. The duty cycle of the second signal is controlled such that a difference between a duty cycle of the first signal and an inverse of the duty cycle of the second signal is less than a tolerance limit.

Abstract: A soft-start circuit for a voltage regulator includes a comparator and a delay circuit. The comparator compares an output voltage, that is generated by the voltage regulator, and a reference voltage to generate a comparison signal. Further, the delay circuit receives the reference voltage and a control signal that is outputted based on the comparison signal, and outputs and provides another reference voltage to the voltage regulator. During a start-up of the voltage regulator, the reference voltage outputted by the delay circuit is a delayed version of the reference voltage received by the delay circuit. Thus, the soft-start circuit mitigates an overshoot of the output voltage during the start-up. Further, on completion of the start-up, the reference voltage outputted by the delay circuit is equal to the reference voltage received by the delay circuit.

Abstract: A bandgap voltage regulator includes a proportional-to-absolute-temperature (PTAT) circuit, an amplifier, and a driver circuit. The PTAT circuit can include various transistors that output a corresponding control voltage. The amplifier generates another control voltage to compensate base-current variations associated with the transistors of the PTAT circuit. The control voltage is generated by the amplifier based on the control voltage outputted by the PTAT circuit, and one of a base-emitter voltage associated with a transistor of the PTAT circuit, a scaled down version of the control voltage outputted by the amplifier, and a scaled down version of the base-emitter voltage. The driver circuit outputs, based on a supply voltage and the control voltages outputted by the PTAT circuit, a reference voltage for driving a functional circuit.

Abstract: A level shifter includes a pull-down circuit, a pull-up circuit, a protection circuit, and an output generator. The pull-down circuit is configured to receive input voltages, and generate bias voltages. The input voltages are associated with a voltage domain. The pull-up circuit is configured to receive a supply voltage and generate control voltages. The protection circuit is configured to receive reference voltages, and control the generation of the bias voltages and the control voltages. The output generator is configured to receive at least one of the reference voltages, and at least one of the bias voltages and the control voltages, and generate output voltages that are able to reach minimum and maximum voltage levels of another voltage domain. Further, the output voltages remain unaffected by variations in process, voltage, and temperature.

Abstract: An integrated circuit includes a base current cancellation circuit and a complementary to absolute temperature (CTAT) circuit. The base current cancellation circuit includes a first bipolar junction transistor (BJT) and a current mirror coupled to the first BJT. The current mirror is configured to provide a mirrored current to a base electrode of the first BJT. The CTAT circuit is coupled to receive a voltage signal corresponding to a reference current of the current mirror. The CTAT circuit includes a second BJT coupled to form a base current based on the voltage signal.

Abstract: An integrated circuit includes an output driver circuit configured to provide a first voltage at an output terminal. The output driver circuit includes a transistor having a first current electrode coupled at a voltage supply terminal and a second current electrode coupled at the output terminal, and a resistor having a first terminal coupled at the output terminal and a second terminal coupled at a first node. An amplifier circuit is coupled to the output driver circuit and is configured to generate a proportional to absolute temperature (PTAT) current in a first circuit branch of the output driver circuit coupled at the first node. A complementary to absolute temperature (CTAT) circuit is configured to generate a CTAT current in a second circuit branch coupled at the first node.

Abstract: A low voltage differential signaling circuit includes an output driver circuit configured to provide a differential signal pair based on a first signal and a second signal. A peak detect circuit is coupled to receive the differential signal pair and configured to provide a feedback signal based on the differential signal pair and the first and second signals. An amplifier circuit has a first input coupled to the peak detect circuit, a second input coupled to receive a reference voltage, and an output coupled to provide a bias voltage to the output driver circuit.

Abstract: An integrated circuit includes a base current cancellation circuit and a complementary to absolute temperature (CTAT) circuit. The base current cancellation circuit includes a first bipolar junction transistor (BJT) and a current mirror coupled to the first BJT. The current mirror is configured to provide a mirrored current to a base electrode of the first BJT. The CTAT circuit is coupled to receive a voltage signal corresponding to a reference current of the current mirror. The CTAT circuit includes a second BJT coupled to form a base current based on the voltage signal.

Abstract: A bandgap circuit has a pair of NPN bipolar devices that are connected to (i) generate a base-to-emitter voltage difference that is applied across an output-stage resistor and (ii) function as input devices for an amplifier stage that ensures that sufficient current is driven across the output-stage resistor to maintain a desired voltage difference. The desired voltage difference, which has a positive temperature coefficient, is combined with a base-to-emitter voltage of another NPN bipolar device having a negative temperature coefficient to provide a bandgap voltage that is substantially impervious to variations in operating temperature, voltage, and process corners. By using the same two bipolar devices to provide two different functions, there is no need for a separate CMOS-based opamp, which reduces the sources of process mismatch that can adversely affect the bandgap voltage compared to conventional bandgap circuits having bipolar devices and a separate CMOS-based opamp.

Abstract: An integrated circuit with a testable power-on-reset (POR) circuit includes a voltage divider, an inverter, a level-shifter, a buffer and a flip-flop. The voltage divider receives a first supply voltage and generates a second supply voltage. The POR circuit receives the second supply voltage and generates a POR voltage signal when the second supply voltage exceeds a POR de-assertion threshold. The level-shifter receives the POR voltage signal and an inverted POR voltage signal from the inverter circuit and generates a level-shifted POR voltage signal at a voltage level of the first supply voltage. The buffer receives the level-shifted POR voltage signal and outputs a delayed level-shifted POR voltage signal. The flip-flop receives the first supply voltage as data input, the delayed level-shifted POR voltage signal as clock input, the level-shifted POR voltage signal as reset input, and outputs a voltage-monitor signal at the voltage level of the first supply voltage.

Abstract: An integrated circuit with a testable power-on-reset (POR) circuit includes a voltage divider, an inverter, a level-shifter, a buffer and a flip-flop. The voltage divider receives a first supply voltage and generates a second supply voltage. The POR circuit receives the second supply voltage and generates a POR voltage signal when the second supply voltage exceeds a POR de-assertion threshold. The level-shifter receives the POR voltage signal and an inverted POR voltage signal from the inverter circuit and generates a level-shifted POR voltage signal at a voltage level of the first supply voltage. The buffer receives the level-shifted POR voltage signal and outputs a delayed level-shifted POR voltage signal. The flip-flop receives the first supply voltage as data input, the delayed level-shifted POR voltage signal as clock input, the level-shifted POR voltage signal as reset input, and outputs a voltage-monitor signal at the voltage level of the first supply voltage.

Abstract: A start-up circuit for a PLL includes a phase-frequency detector (PFD), one or more logic gates, a flip-flop and a false detection circuit. The false detection circuit includes a set of series connected flip-flops. The PFD receives a reference signal and a feedback signal. The PFD compares the frequency of a reference signal with that of a feedback signal. If the frequency of the reference signal is greater than the frequency of the feedback signal then a start-up signal is generated and transmitted to the PLL. The PLL increases the frequency of the feedback signal until it is greater than the frequency of the reference signal. The generation of the start-up signal is halted when the frequency of the feedback signal is greater than the frequency of the reference signal.

Abstract: A duty cycle correction circuit for correcting the duty cycle of a clock signal generated by a clock generator includes a complementary buffer chain, level shifter circuits and a self-bias circuit. A clock signal with a distorted duty cycle and its complement are provided to the level shifter circuits. The level shifter circuits reduce the magnitude of voltage of the clock signal and the complement and generate level shifted signals. The level shifted signals are provided to a differential amplifier that generates a control signal indicating the magnitude of distortion in the duty cycle. The control signal is used to correct the duty cycle of the clock signal. The self-bias circuit is used to bias the differential amplifier.

Abstract: A start-up circuit for a PLL includes a phase-frequency detector (PFD), one or more logic gates, a flip-flop and a false detection circuit. The false detection circuit includes a set of series connected flip-flops. The PFD receives a reference signal and a feedback signal. The PFD compares the frequency of a reference signal with that of a feedback signal. If the frequency of the reference signal is greater than the frequency of the feedback signal then a start-up signal is generated and transmitted to the PLL. The PLL increases the frequency of the feedback signal until it is greater than the frequency of the reference signal. The generation of the start-up signal is halted when the frequency of the feedback signal is greater than the frequency of the reference signal.

Abstract: A duty cycle correction circuit for correcting the duty cycle of a clock signal generated by a clock generator includes a complementary buffer chain, level shifter circuits and a self-bias circuit. A clock signal with a distorted duty cycle and its complement are provided to the level shifter circuits. The level shifter circuits reduce the magnitude of voltage of the clock signal and the complement and generate level shifted signals. The level shifted signals are provided to a differential amplifier that generates a control signal indicating the magnitude of distortion in the duty cycle. The control signal is used to correct the duty cycle of the clock signal. The self-bias circuit is used to bias the differential amplifier.

Abstract: A brown out detector includes a first resistive element connected to a first voltage and a first node. A capacitor is connected to the first node and a second voltage. The detector also includes a second transistor and a third transistor. The second transistor has a drain connected to a second node, a source connected to the first node, and a gate connected to the first voltage. The third transistor has a source connected to the second voltage and the capacitor, a drain connected to the second node, and a gate connected to the first voltage. The detector also includes a latch having an input connected to the second node and a detector output, which generates a reset signal when the first voltage is less than a detection threshold voltage.