Abstract: The present application relates to a method of fabricating planar circuits using a photo lithographic mask set, to the photo lithographic mask set, and to a planar circuit fabricated with the photo lithographic mask set. The instant invention involves separating a photo lithographic mask into two parts, namely, a master mask and one or more slave masks. The master mask and the one or more slave masks form a photo lithographic mask set that is used iteratively to fabricate the planar circuits. In particular, the master mask is used as a template to provide the general layout for the planar circuit, while each slave mask is varied to tune and/or tailor the planar circuit. Since only a small portion of the planar circuit is redesigned and/or rewritten as a new mask (i.e., the slave mask), the instant invention provides a simple and cost effective method for optimizing planar circuits.

Abstract: The invention relates to a variable optical attenuator constructed as a Mach Zehnder planar lightwave circuit, particularly including a channel waveguide support structure for heat isolation and stress relief to reduce polarization dependent loss (PDL) and power consumption in the device. Power reduction trenches comprise longitudinal segments having small stress relief pillars of cladding material left in between them in the etching process. The waveguides of the MZI are supported by a main pillar structure and integral stress relief pillars which remain after removal of the trenches. The waveguide is surrounded by air on three sides for improved heat isolation. The performance of the present invention shows substantial improvement in PDL and extinction ratio over the prior art continuous trench design, and also, to a smaller degree, over the case where power reduction trenches are not used at all.

Abstract: A planar lightwave circuit includes at least one optical waveguide core, and at least one feature proximate the core having a stress-engineered property to balance stress and therefore minimize birefringence affecting the core. A protective passivation layer is formed over the core and the feature to be substantially non-interfering with the balanced stress provided by the feature. The stress balancing feature may be an overcladding layer formed over the core, doped to have a coefficient of thermal expansion approximately matched to that of an underlying substrate, to symmetrically distribute stress in an undercladding between the overcladding and the substrate, away from the core. The protective passivation layer is formed to have a coefficient of thermal expansion approximately matched to that of the overcladding. In one exemplary embodiment, the passivation layer is formed from silicon nitride. Related concepts of stress release grooves, and core overetching, are also disclosed.

Abstract: Micro devices are formed in situ in a high density in a substrate comprising a masked silicon layer over a stop layer of a silicon compound, by anisotropically etching the desired feature in the silicon layer, overetching to form a notch at the silicon-stop layer interface, depositing a protective fluorocarbon polymer layer on the sidewalls and bottom of the etched silicon layer, and isotropically etching to separate the etched feature from the stop layer. This method avoids the problems of stiction common in other methods of forming micro devices.

Abstract: Micro devices are formed in situ in a high density in a substrate comprising a masked silicon layer over a stop layer of a silicon compound, by anisotropically etching the desired feature in the silicon layer, overetching to form a notch at the silicon-stop layer interface, depositing a protective fluorocarbon polymer layer on the sidewalls and bottom of the etched silicon layer, and isotropically etching to separate the etched feature from the stop layer. This method avoids the problems of stiction common in other methods of forming micro devices.

Abstract: A planar lightwave circuit includes an arrayed waveguide grating (AWG), with input and output waveguides, partially curved array waveguides with respective length differences, and planar waveguide regions for focusing optical energy between the input/output and array waveguides. Optimal waveguide widths and spacing along the planar waveguide region facets are disclosed, which are largely determinative of AWG size and optical performance. Also disclosed are optimal cross-sectional waveguide dimensions (e.g., width and height); modified index of refraction difference between the waveguide core and cladding regions; and optimal array waveguide lengths, path length differences, and free spectral range. These features, especially when combined with advanced fiber attachment, passivation and packaging techniques, result in high-yield, high-performance AWGs (both gaussian and flattop versions).

Abstract: A planar lightwave circuit includes an arrayed waveguide grating (AWG), with input and output waveguides, partially curved array waveguides with respective length differences, and planar waveguide regions for focusing optical energy between the input/output and array waveguides. Optimal waveguide widths and spacing along the planar waveguide region facets are disclosed, which are largely determinative of AWG size and optical performance. Also disclosed are optimal cross-sectional waveguide dimensions (e.g., width and height); modified index of refraction difference between the waveguide core and cladding regions; and optimal array waveguide lengths, path length differences, and free spectral range. These features, especially when combined with advanced fiber attachment, passivation and packaging techniques, result in high-yield, high-performance AWGs (both gaussian and flattop versions).

Abstract: A planar lightwave circuit includes at least one optical waveguide core, and at least one feature proximate the core having a stress-engineered property to balance stress and therefore minimize birefringence affecting the core. A protective passivation layer is formed over the core and the feature to be substantially non-interfering with the balanced stress provided by the feature. The stress balancing feature may be an overcladding layer formed over the core, doped to have a coefficient of thermal expansion approximately matched to that of an underlying substrate, to symmetrically distribute stress in an undercladding between the overcladding and the substrate, away from the core. The protective passivation layer is formed to have a coefficient of thermal expansion approximately matched to that of the overcladding. In one exemplary embodiment, the passivation layer is formed from silicon nitride. Related concepts of stress release grooves, and core overetching, are also disclosed.