Abstract: An efficient delay locked loop (DLL) training protocol during a frequency change includes an integrated circuit with a memory physical layer (PHY) unit that includes a master DLL and a slave DLL. The master DLL may delay a first reference clock by an amount, and provide a reference delay value corresponding to the delay amount. The slave DLL may delay a second reference clock by a second amount based upon a received configuration delay value. An interface unit may generate the configuration delay value based upon the reference delay value. A power management unit may provide an indication that the frequency of the second reference clock is changing. In response to receiving the indication, the interface unit may generate a new configuration delay value that corresponds to the new frequency using a predetermined scaling value and provide the new configuration delay value to the memory PHY unit.

Abstract: A PIO transaction unit includes an input buffer, a response buffer, and a control unit. The input buffer may receive and store PIO write operations sent by one or more transactions sources. Each PIO write operation may include a source identifier that identifies the transaction source. The response buffer may store response operations corresponding to respective PIO write operations that are to be transmitted to the transaction source identified by the source identifier. The control unit may store a particular response operation corresponding to the given PIO write operation in the response buffer prior to the given PIO write operation being sent from the input buffer. The control unit may store the particular response operation within the response buffer if the given PIO write operation is bufferable and there is no non-bufferable PIO write operation having a same source identifier stored in the input buffer.

Abstract: A delay locked loop (DLL) having an accelerated training interval during a voltage change. An integrated circuit (IC) includes a master DLL configured to generate a clock signal based upon a reference clock signal. The master DLL may train to the reference clock signal in response to a control signal. The IC also includes a control unit that is coupled to the master DLL and may provide the control signal at a first interval in response to receiving an indication that a supply voltage is being changed, and provide the control signal at a second interval in the absence of the indication.

Abstract: An efficient delay locked loop (DLL) training protocol during a frequency change includes an integrated circuit with a memory physical layer (PHY) unit that includes a master DLL and a slave DLL. The master DLL may delay a first reference clock by an amount, and provide a reference delay value corresponding to the delay amount. The slave DLL may delay a second reference clock by a second amount based upon a received configuration delay value. An interface unit may generate the configuration delay value based upon the reference delay value. A power management unit may provide an indication that the frequency of the second reference clock is changing. In response to receiving the indication, the interface unit may generate a new configuration delay value that corresponds to the new frequency using a predetermined scaling value and provide the new configuration delay value to the memory PHY unit.

Abstract: A delay locked loop (DLL) having an accelerated training interval during a voltage change. An integrated circuit (IC) includes a master DLL configured to generate a clock signal based upon a reference clock signal. The master DLL may train to the reference clock signal in response to a control signal. The IC also includes a control unit that is coupled to the master DLL and may provide the control signal at a first interval in response to receiving an indication that a supply voltage is being changed, and provide the control signal at a second interval in the absence of the indication.

Abstract: A PIO transaction unit includes an input buffer, a response buffer, and a control unit. The input buffer may receive and store PIO write operations sent by one or more transactions sources. Each PIO write operation may include a source identifier that identifies the transaction source. The response buffer may store response operations corresponding to respective PIO write operations that are to be transmitted to the transaction source identified by the source identifier. The control unit may store a particular response operation corresponding to the given PIO write operation in the response buffer prior to the given PIO write operation being sent from the input buffer. The control unit may store the particular response operation within the response buffer if the given PIO write operation is bufferable and there is no non-bufferable PIO write operation having a same source identifier stored in the input buffer.

Abstract: In one embodiment, an integrated circuit includes a processor, an internal memory, and a memory controller coupled to an external memory. The integrated circuit may support two or more modes of operation, with different operating points. To switch from one operating point to another, code executed by the processor may copy switch code from the external memory into the internal memory, and may jump to the switch code. Executing out of the internal memory, the switch code may communicate with the memory controller to cause the external memory to enter into self-refresh mode. The operating point may be altered, and the switch code may reinitialize the memory controller after the integrated circuit has stabilized at the new operating point. After the memory controller's physical interface circuit has relocked, the external memory may exit self-refresh mode.

Abstract: A PIO transaction unit includes an input buffer, a response buffer, and a control unit. The input buffer may receive and store PIO write operations sent by one or more transactons sources. Each PIO write operation may include a source identifier that identifies the transaction source. The response buffer may store response operations corresponding to respective PIO write operations that are to be transmitted to the transaction source identified by the identifier. The control unit may store a particular response operation corresponding to the given PIO write operation in the response buffer prior to the given PIO write operation being sent from the input buffer. The control unit may store the particular response operation within the response buffer if the given PIO write operation is bufferable and there is no non-bufferable PIO write operation having a same source identifier stored in the input buffer.

Abstract: A PIO transaction unit includes an input buffer, a response buffer, and a control unit. The input buffer may receive and store PIO write operations sent by one or more transactions sources. Each PIO write operation may include a source identifier that identifies the transaction source. The response buffer may store response operations corresponding to respective PIO write operations that are to be transmitted to the transaction source identified by the source identifier. The control unit may store a particular response operation corresponding to the given PIO write operation in the response buffer prior to the given PIO write operation being sent from the input buffer. The control unit may store the particular response operation within the response buffer if the given PIO write operation is bufferable and there is no non-bufferable PIO write operation having a same source identifier stored in the input buffer.

Abstract: In one embodiment, an integrated circuit includes a processor, an internal memory, and a memory controller coupled to an external memory. The integrated circuit may support two or more modes of operation, with different operating points. To switch from one operating point to another, code executed by the processor may copy switch code from the external memory into the internal memory, and may jump to the switch code. Executing out of the internal memory, the switch code may communicate with the memory controller to cause the external memory to enter into self-refresh mode. The operating point may be altered, and the switch code may reinitialize the memory controller after the integrated circuit has stabilized at the new operating point. After the memory controller's physical interface circuit has relocked, the external memory may exit self-refresh mode.

Abstract: A computer. When an instruction calling for an architecturally-visible side-effect in an architecturally-visible storage location is recognized, a value is stored representative of an architecturally-visible representation of the side-effect, a format of the representative value being different than an architecturally-visible representation of the side-effect. Execution is resumed without generating the architecturally-visible side-effect. Later, the architecturally-visible representation corresponding to the representative value is written into the architecturally-visible storage location. On a context switch, a context of a first process is written and a context of a second process is loaded to place the second process into execution. At least some instructions maintain results in storage resources outside the context resource set, and instructions are marked to indicate whether or not a context switch may be performed at a boundary of the marked instruction.

Abstract: An apparatus that provides configurable processing includes a fetch module, a decoder, and a dynamic arithmetic unit. The fetch module is operable to fetch at least one instruction and provide it to the decoder. The decoder receives the instruction and decodes it. The dynamic arithmetic logic unit receives the decoded instruction and configures at least one configurable arithmetic logic unit to perform an operation contained within the decoded instruction.

Abstract: A floating point register stack for a processor combines a plurality of two general purpose registers to form a register stack for x86 instructions and leaves the remaining general purpose registers for native instructions of the processor. By mapping x86 sources into the stack of two general purpose registers and operating x86 instructions on the x86 stack, the register stack for the processor is able to support both the processor's native instruction set and the x86 instruction set without increasing the size of the register stack.

Abstract: A floating point arithmetic logic unit includes two rounding units that select between an incremented, unincremented, and complemented result from a carry propagate adder. A fast rounding unit selects a result as an approximation based on the equality or inequality of the exponents of the operands, the relative sizes of the mantissas and the presence of a guard bit. The result selected by the fast rounding unit is received by a leading zero count unit, which counts the leading zeros of the result. A second slower rounding unit meanwhile makes a selection between the incremented, unincremented, and complemented results based on the rounding mode, the sign of the result and whether the result is exact. The result is inexact when both the most significant bit and the guard bit are equal to one. While the slower rounding unit may take longer to determine the appropriate selection, the result selected is the most accurate.

Abstract: A floating point unit includes a rounding unit that rounds the two least significant bits of a sum. After a sum of the two mantissas is generated the at least one least significant bit is separated from the sum. When addition is performed, two least significant bits are separated from the sum. A half add unit may be used to generate the sum along with a set of carry data, and thus at least one least significant bit of the carry data is also separated. A rounding unit receives the separated at least one least significant bit of the sum and carry data and produces a carry in bit as well as rounded at least one least significant bit. The sum and carry data are then summed in a later stage of the floating point unit to form both a unincremented sum and an incremented sum, which are stored in a multiplexer. The carry in bit is used to select one of the unincremented sum and incremented sum.

Abstract: A double incrementing adder includes an AND gate configured to receive bits of the two input values of a common weight (“first weight”). The AND gate has an output terminal configured to carry the AND'ed bit. A three input XOR gate is configured to receive bits of the two input values of a common weight (“second weight”) one bit more significant than the first weight. The three input XOR gate is configured to XOR these values with the AND'ed bit to generate a three input XOR'ed bit.