Patents by Inventor Sanjay Mitra

Sanjay Mitra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9835716
    Abstract: A sensor comprising a light emitter and light detector directly covered and encapsulated by a layer of light blocking compound. The light blocking compound can be thick enough between the light emitter and light detector to block substantially all light emitted by the light emitter from reaching the light detector directly, but be thin enough above the light emitter and light detector to allow at least some level of light emitted by the light emitter to escape out of the sensor, be reflected by another object, re-enter the sensor, and survive passing through the light blocking compound to enter the light detector.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: December 5, 2017
    Assignee: Hana Microelectronics, Inc.
    Inventors: Vanapong Kwangkaew, Krisadayut Chansawang, Sirirat Silapapipat, Preecha Bootwicha, Sanjay Mitra
  • Patent number: 9824401
    Abstract: The present invention is directed to a system that updates files with updated financial data. The system of the present invention is configured to receive from a user one or more selections of files (e.g., datastores of financial data utilized and/or referenced by financial reporting application for purposes of generating up-to-date financial reports) to be updated with updated financial data. The user is further enabled by the system of the present invention to schedule importations of updated financial data into each selected file. The system of the present invention also is configured to generate a report of complete file updates so that the user may more effectively monitor and review the file-updating processes.
    Type: Grant
    Filed: January 1, 2015
    Date of Patent: November 21, 2017
    Assignee: BANK OF AMERICA CORPORATION
    Inventors: Sanjay Mitra, Shveta Mittal, Kunal Jain
  • Patent number: 9632209
    Abstract: A sensor comprising a light emitter and light detector directly covered and encapsulated by a layer of light blocking compound. The light blocking compound can be thick enough between the light emitter and light detector to block substantially all light emitted by the light emitter from reaching the light detector directly, but be thin enough above the light emitter and light detector to allow at least some level of light emitted by the light emitter to escape out of the sensor, be reflected by another object, re-enter the sensor, and survive passing through the light blocking compound to enter the light detector.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: April 25, 2017
    Assignee: Hana Microelectronics, Inc.
    Inventors: Vanapong Kwangkaew, Krisadayut Chansawang, Sirirat Silapapipat, Preecha Bootwicha, Sanjay Mitra
  • Publication number: 20170067986
    Abstract: A sensor comprising a light emitter and light detector directly covered and encapsulated by a layer of light blocking compound. The light blocking compound can be thick enough between the light emitter and light detector to block substantially all light emitted by the light emitter from reaching the light detector directly, but be thin enough above the light emitter and light detector to allow at least some level of light emitted by the light emitter to escape out of the sensor, be reflected by another object, re-enter the sensor, and survive passing through the light blocking compound to enter the light detector.
    Type: Application
    Filed: September 9, 2016
    Publication date: March 9, 2017
    Inventors: Vanapong Kwangkaew, Krisadayut Chansawang, Sirirat Silapapipat, Preecha Bootwicha, Sanjay Mitra
  • Publication number: 20160282510
    Abstract: A sensor comprising a light emitter and light detector directly covered and encapsulated by a layer of light blocking compound. The light blocking compound can be thick enough between the light emitter and light detector to block substantially all light emitted by the light emitter from reaching the light detector directly, but be thin enough above the light emitter and light detector to allow at least some level of light emitted by the light emitter to escape out of the sensor, be reflected by another object, re-enter the sensor, and survive passing through the light blocking compound to enter the light detector.
    Type: Application
    Filed: March 25, 2015
    Publication date: September 29, 2016
    Applicant: HANA MICROELECTRONICS, INC.
    Inventors: Vanapong Kwangkaew, Krisadayut Chansawano, Sirirat Silapapipat, Preecha Bootwicha, Sanjay Mitra
  • Patent number: 9442216
    Abstract: A sensor comprising a light emitter and light detector directly covered and encapsulated by a layer of light blocking compound. The light blocking compound can be thick enough between the light emitter and light detector to block substantially all light emitted by the light emitter from reaching the light detector directly, but be thin enough above the light emitter and light detector to allow at least some level of light emitted by the light emitter to escape out of the sensor, be reflected by another object, re-enter the sensor, and survive passing through the light blocking compound to enter the light detector.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: September 13, 2016
    Assignee: HANA MICROELECTRONICS, INC.
    Inventors: Vanapong Kwangkaew, Krisadayut Chansawang, Sirirat Silapapipat, Preecha Bootwicha, Sanjay Mitra
  • Publication number: 20160196614
    Abstract: The present invention is directed to a system that updates files with updated financial data. The system of the present invention is configured to receive from a user one or more selections of files (e.g., datastores of financial data utilized and/or referenced by financial reporting application for purposes of generating up-to-date financial reports) to be updated with updated financial data. The user is further enabled by the system of the present invention to schedule importations of updated financial data into each selected file. The system of the present invention also is configured to generate a report of complete file updates so that the user may more effectively monitor and review the file-updating processes.
    Type: Application
    Filed: January 1, 2015
    Publication date: July 7, 2016
    Inventors: Sanjay Mitra, Shveta Mittal, Kunal Jain
  • Patent number: 6232153
    Abstract: A plastic package assembly method suitable for ferroelectric-based integrated circuits includes a strict thermal budget that reduces the time at temperature for four key processing steps: die attach cures, die coat cures, molding cures, and marking cures. The plastic package assembly method uses low temperature mold and die coat materials, as well as low temperature curable inks or laser marking in order to minimize degradation of electrical performance, thus improving yields and reliability. The assembly method uses a snap cure die attach step, a die coat followed by a room temperature cure, and formation of the plastic package with room temperature curable molding compounds not requiring a post mold cure. Front and back marking of the plastic package is accomplished using either an infrared or ultraviolet curable ink followed by minimum cure time at elevated temperature, or by using laser marking.
    Type: Grant
    Filed: June 4, 1998
    Date of Patent: May 15, 2001
    Assignee: Ramtron International Corporation
    Inventors: Sanjay Mitra, Vic Lau
  • Patent number: 6190926
    Abstract: A yield enhancement technique for integrated circuit processing which reduces the deleterious effects of H2O contamination which is absorbed by conventional dielectric films resulting in an undesired subsequent out-diffusion of hydrogen when the integrated circuit die is subsequently subjected to relatively high processing temperatures such as those experienced in CERDIP packaging. The technique disclosed comprises the formation of an interlevel dielectric layer having hydrophilic properties (for example, 7.5% phosphorus doped TEOS) at least partially surrounding a device on the integrated circuit which layer is then subjected to an annealing operation to drive off at least a portion of any moisture present therein.
    Type: Grant
    Filed: July 19, 1999
    Date of Patent: February 20, 2001
    Assignee: Ramtron International Corporation
    Inventors: Stanley C. Perino, Sanjay Mitra, George Argos, Jr., Holli Harper
  • Patent number: 5990513
    Abstract: A yield enhancement technique for integrated circuit processing which reduces the deleterious effects of H.sub.2 O contamination which is absorbed by conventional dielectric films resulting in an undesired subsequent out-diffusion of hydrogen when the integrated circuit die is subsequently subjected to relatively high processing temperatures such as those experienced in CERDIP packaging. The technique disclosed comprises the formation of an interlevel dielectric layer having hydrophilic properties (for example, 7.5% phosphorus doped TEOS) at least partially surrounding a device on the integrated circuit which layer is then subjected to an annealing operation to drive off at least a portion of any moisture present therein.
    Type: Grant
    Filed: October 8, 1996
    Date of Patent: November 23, 1999
    Assignee: Ramtron International Corporation
    Inventors: Stanley C. Perino, Sanjay Mitra, George Argos, Jr., Holli Harper
  • Patent number: 5661730
    Abstract: A test method for ferroelectric memories includes the steps of: functionally testing the ferroelectric memories to determine functional yield; storing the ferroelectric memories for at least eight hours; writing an initial pattern into the ferroelectric memories; baking the ferroelectric memories; reading the initial pattern to determine same state yield; writing an inverse pattern into the ferroelectric memories; reading the inverse pattern to determine opposite state yield; and again writing the initial pattern into the ferroelectric memories. The steps of baking, reading the initial pattern and writing the inverse pattern, and reading the inverse pattern and writing the initial pattern are repeated for a number of test cycles. The ferroelectric memories are baked at a temperature of about 150.degree. C. for a predetermined duration that is incremented with each successive test cycle.
    Type: Grant
    Filed: September 27, 1996
    Date of Patent: August 26, 1997
    Assignee: Ramtron International Corporation
    Inventors: Sanjay Mitra, Holden Hackbarth
  • Patent number: 5525528
    Abstract: Ferroelectric capacitors in an integrated memory are renewed to improve retention performance. The renewal method is performed on a wafer containing ferroelectric memory die. In one method, a rejuvenation anneal is performed after all electrical tests, including those at elevated temperatures, have been accomplished, but before the failed die have been inked. The rejuvenation anneal is performed at or above the Curie temperature of the ferroelectric material. In the preferred embodiment, the ferroelectric material is PZT, and the rejuvenation anneal is a thermal treatment at 400.degree. Centigrade in a nitrogen flow of roughly ten liters per minute for about an hour. In another method, separate electrical cycling and depoling operations are performed to provide the equivalent benefits of the single rejuvenation anneal. The electrical cycling operation is accomplished by writing about one hundred cycles at five volts alternating logic states into each ferroelectric capacitor into the array.
    Type: Grant
    Filed: February 23, 1994
    Date of Patent: June 11, 1996
    Assignee: Ramtron International Corporation
    Inventors: Stanley Perino, Sanjay Mitra