Abstract: A system that includes a regulator circuit is disclosed. The regulator circuit includes first and second phase units whose outputs are coupled to a power supply node of a circuit block, via respective coupled inductors. The first phase unit may initiate a charge cycle of the power supply node in response to assertion of a clock signal and generate a compensated current using currents measure through both inductors and the clock signal. In response to a determination that the compensated current is greater than a demand current generated using a voltage level of the power supply node and a reference voltage, the first phase unit may halt the charge cycle.

Abstract: A system that includes a regulator unit is disclosed. The regulator unit includes first and second phase units whose outputs are coupled to through first and second coupled inductors, respectively, to a power supply node of a circuit block. The first phase unit may be configured to discharge, for a first period of time, the power supply node through the first inductor in response to determining a sense current is greater than a demand current. The operation of the second phase unit may follow that of the first phase unit after a second period of time has elapsed.

Abstract: A method for regulating voltage for a processor is disclosed. The method comprises requesting a target frequency value, wherein the target frequency value determines a target clock frequency for clocking the processor. The method also comprises comparing the target clock frequency to a first signal to generate an error signal. Further, the method comprises using the error signal to generate a duty cycle control signal, wherein the duty cycle control signal is operable to generate a periodic waveform. Finally, the method comprises generating an output regulator voltage using the periodic waveform, wherein the output voltage is operable to provide power to the processor.

Abstract: A system that includes a regulator circuit is disclosed. The regulator circuit includes first and second phase units whose outputs are coupled to a power supply node of a circuit block, via respective coupled inductors. The first phase unit may initiate a charge cycle of the power supply node in response to assertion of a clock signal and generate a compensated current using currents measure through both inductors and the clock signal. In response to a determination that the compensated current is greater than a demand current generated using a voltage level of the power supply node and a reference voltage, the first phase unit may halt the charge cycle.

Abstract: A system that includes a regulator unit is disclosed. The regulator unit includes first and second phase units whose outputs are coupled to through first and second coupled inductors, respectively, to a power supply node of a circuit block. The first phase unit may be configured to discharge, for a first period of time, the power supply node through the first inductor in response to determining a sense current is greater than a demand current. The operation of the second phase unit may follow that of the first phase unit after a second period of time has elapsed.

Abstract: Techniques are disclosed relating to detecting supply voltage events and performing corrective actions. In some embodiments, an apparatus includes sensor circuitry and control circuitry. In some embodiments, the sensor circuitry is configured to monitor supply voltage from a power supply and detect a load release event that includes an increase in the supply voltage that meets one or more pre-determined threshold parameters. In some embodiments, the control circuitry is configured to increase clock cycle time for operations performed by circuitry powered by the supply voltage during a time interval, wherein the time interval corresponds to ringing of the supply voltage that reduces the supply voltage and results from the load release event. In some embodiments, the disclosed techniques may reduce transients in supply voltage (which may avoid equipment damage and computing errors) and may allow for reduced voltage margins (which may reduce overall power consumption).

Abstract: Techniques are disclosed relating to rapidly downshifting the output frequency of an oscillator. In some embodiments, the oscillator is configured to operate in a closed-loop mode in which negative feedback is used to maintain a particular output frequency (e.g., in a phase-locked loop (PLL)). In some embodiments, the negative feedback loop is configured to maintain the output of the oscillator at a particular frequency based on a reference clock signal and the output of the oscillator. The nature of a negative feedback loop may render rapid frequency changes difficult, e.g., because of corrections by the loop. Therefore, in some embodiments, the loop is configured to switch to an open-loop mode in which a control input to the oscillator is fixed. In some embodiments, the loop switches to open-loop mode in response to a trigger signal and control circuitry forces the oscillator to a new target frequency.

Abstract: A method for regulating voltage for a processor is disclosed. The method comprises requesting a target frequency value, wherein the target frequency value determines a target clock frequency for clocking the processor. The method also comprises comparing the target clock frequency to a first signal to generate an error signal. Further, the method comprises using the error signal to generate a duty cycle control signal, wherein the duty cycle control signal is operable to generate a periodic waveform. Finally, the method comprises generating an output regulator voltage using the periodic waveform, wherein the output voltage is operable to provide power to the processor.

Abstract: A tubular stent has first and second ends and a longitudinal axis therebetween. The tubular stent is formed from a network of struts which defines a cylindrical surface about the longitudinal axis, the struts delineating a plurality of cells within the network, there being rows of cells parallel to the longitudinal axis. At least one cell in each row is a nodal cell. There is an increase in the maximum length parallel to the longitudinal axis of cells from the nodal cell to a first distal cell in the row that is closer to the first or second end of the tubular stent. There is a second distal cell in the row which has a different maximum length parallel to the longitudinal axis from the nodal cell and the first distal cell. The network of struts comprises a plurality of circumferential rings. Each ring extends perpendicularly to the longitudinal axis and the rings are located adjacent to each other parallel to the longitudinal axis to define the cylindrical surface.

Abstract: A system that includes a regulator unit is disclosed. The regulator unit includes first and second phase units whose outputs are coupled to a common output node. Each of the phase units may be configured to source current to the output node in response to the assertion of a respective clock signal in order to generate a regulated supply voltage. Each phase unit includes a respective transconductance amplifier configured to generate a respective demand current dependent upon a reference voltage and the regulated supply voltage.

Abstract: A method for regulating voltage for a processor is disclosed. The method comprises requesting a target frequency value, wherein the target frequency value determines a target clock frequency for clocking the processor. The method also comprises comparing the target clock frequency to a first signal to generate an error signal. Further, the method comprises using the error signal to generate a duty cycle control signal, wherein the duty cycle control signal is operable to generate a periodic waveform. Finally, the method comprises generating an output regulator voltage using the periodic waveform, wherein the output voltage is operable to provide power to the processor.

Abstract: In an embodiment, a supply voltage envelope detector circuit is configured to detect a shape of the supply voltage over time and to compare the detected shape to expected shapes that indicate voltage droop events for which corrective action may be needed. The expected shapes may be predetermined based on one or more of: the design of the integrated circuit that includes the supply voltage envelope detector circuit; attributes of the power management unit (PMU) that is to generate the supply voltage for the integrated circuit; and/or attributes of the system that includes the integrated circuit. The shape of the voltage droop may experience little variation during use, and thus may be used to detect a droop event earlier and more accurately than a threshold-based mechanism, in some embodiments.

Abstract: A multi-core data processor includes multiple data processor cores and a circuit. The multiple data processor cores each include a power state controller having a first input for receiving an idle signal, a second input for receiving a release signal, a third input for receiving a control signal, and an output for providing a current power state. In response to the idle signal, the power state controller causes a corresponding data processor core to enter an idle state. In response to the release signal, the power state controller changes the current power state from the idle state to an active state in dependence on the control signal. The circuit is coupled to each of the multiple data processor cores for providing the control signal in response to current power states in the multiple data processor cores.

Abstract: A tubular stent has first and second ends and a longitudinal axis therebetween. The tubular stent is formed from a network of struts which defines a cylindrical surface about the longitudinal axis, the struts delineating a plurality of cells within the network, there being rows of cells parallel to the longitudinal axis. At least one cell in each row is a nodal cell. There is an increase in the maximum length parallel to the longitudinal axis of cells from the nodal cell to a first distal cell in the row that is closer to the first or second end of the tubular stent. There is a second distal cell in the row which has a different maximum length parallel to the longitudinal axis from the nodal cell and the first distal cell. The network of struts comprises a plurality of circumferential rings. Each ring extends perpendicularly to the longitudinal axis and the rings are located adjacent to each other parallel to the longitudinal axis to define the cylindrical surface.

Abstract: A tubular stent (1) has first and second ends (2,3) and a longitudinal axis (4) therebetween. The tubular stent (1) is formed from a network of struts which defines a cylindrical surface about the longitudinal axis (4), the struts delineating a plurality of cells {23, 30, 31, 32, 33) within the network, there being rows of cells parallel to the longitudinal axis (4). At least one cell in each row is a nodal cell (23). There is an increase in the maximum length parallel to the longitudinal axis (4) of cells from the at least one nodal cell (23) to a first distal cell (30) in the row that is closer to the first or second end (2, 3) of the tubular stent (1). There is a second distal cell (31) in the row which has a different maximum length parallel to the longitudinal axis (4) from the nodal cell (23) and the first distal cell (30). The network of struts comprises a plurality of circumferential rings (6, 6?, 9, 9?, 13, 13?, 16, 16?, 17, 17?).

Abstract: A multi-core data processor includes multiple data processor cores and a power controller. Each data processor core has a first input for receiving a clock signal, a second input for receiving a power supply voltage, and an output for providing an idle signal. The power controller is coupled to each of the data processor cores for providing the clock signal and the power supply voltage to each of the data processor cores. The power controller provides at least one of the clock signal and the power supply voltage to an active one of the data processor cores in dependence on a number of idle signals received from the data processor cores.

Abstract: A multi-core data processor includes multiple data processor cores and a circuit. The multiple data processor cores each include a power state controller having a first input for receiving an idle signal, a second input for receiving a release signal, a third input for receiving a control signal, and an output for providing a current power state. In response to the idle signal, the power state controller causes a corresponding data processor core to enter an idle state. In response to the release signal, the power state controller changes the current power state from the idle state to an active state in dependence on the control signal. The circuit is coupled to each of the multiple data processor cores for providing the control signal in response to current power states in the multiple data processor cores.

Abstract: A multi-core data processor includes multiple data processor cores and a power controller. Each data processor core has a first input for receiving a clock signal, a second input for receiving a power supply voltage, and an output for providing an idle signal. The power controller is coupled to each of the data processor cores for providing the clock signal and the power supply voltage to each of the data processor cores. The power controller provides at least one of the clock signal and the power supply voltage to an active one of the data processor cores in dependence on a number of idle signals received from the data processor cores.

Abstract: A tubular stent (1) has first and second ends (2,3) and a longitudinal axis (4) therebetween. The tubular stent (1) is formed from a network of struts which defines a cylindrical surface about the longitudinal axis (4), the struts delineating a plurality of cells {23, 30, 31, 32, 33) within the network, there being rows of cells parallel to the longitudinal axis (4). At least one cell in each row is a nodal cell (23). There is an increase in the maximum length parallel to the longitudinal axis (4) of cells from the at (east one nodal cell (23) to a first distal cell (30) in the row that is closer to the first or second end (2, 3) of the tubular stent (1). There is a second distal cell (31) in the row which has a different maximum length parallel to the longitudinal axis (4) from the nodal cell (23) and the first distal cell (30). The network of struts comprises a plurality of circumferential rings (6, 6?, 9, 9?, 13, 13?, 16, 16?, 17, 17?).

Abstract: A clock frequency of a clock signal used by a processor may be temporarily reduced to compensate for voltage droops in the power supply to the processor. A device may include a multiplexer to receive a group of phase shifted versions of the clock signal and to output one of the group of phase shifted versions of the clock signal as an output clock signal. A control component may receive the output clock signal from the multiplexer and a voltage droop event signal indicating whether a voltage droop event is occurring in a power supply. The control component may control, in response to the voltage droop event signal indicating the occurrence of the voltage droop event, the multiplexer to iteratively select the group of phase shifted versions of the clock signal to reduce the frequency of the output clock signal.