Patents by Inventor Sanjay Pennam
Sanjay Pennam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11689316Abstract: A transmitter includes a data stream encoder layer having an output and a pattern generator having a bit pattern output. The transmitter further includes a first multiplexer having first and second inputs and a first multiplexer output. The first input is coupled to the output of the data stream encoder layer, and the second input is coupled to the bit pattern output of the pattern generator. While at least a portion of the data stream encoder layer is powered down, the pattern generator is configured to provide bit patterns on its bit pattern output, a control signal to the first multiplexer is configured to select the second input of the first multiplexer, and the first multiplexer is configured to output the bit patterns on the output of the first multiplexer.Type: GrantFiled: August 31, 2021Date of Patent: June 27, 2023Assignee: Texas Instruments IncorporatedInventors: Sanjay Pennam, Vamsi Krishna Kandalla, Brahmendra Reddy Yatham, Shailesh Wardhen, Jaiganesh Balakrishnan, Jawaharlal Tangudu
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Publication number: 20220271762Abstract: A system for generating secondary clock signals from a primary clock signal includes a dithered clock divider which has a first input adapted to receive the primary clock signal and a second input adapted to receive a random division ratio. The dithered clock divider provides a dithered clock signal. The system includes a multi-phase clock generator which has a first input adapted to receive the primary clock signal, a second input adapted to receive the dithered clock signal, and a third input adapted to receive a pseudo-random pattern. The multi-phase clock generator provides the secondary clock signals from multiple phases of the dithered clock signal. The system includes a pseuodo-random pattern generator which provides the pseudo-random pattern.Type: ApplicationFiled: September 29, 2021Publication date: August 25, 2022Inventors: Aswath Vs, Sundarrajan Rangachari, Sarma Sundareswara Gunturi, Sanjay Pennam
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Patent number: 11422586Abstract: A system for generating secondary clock signals from a primary clock signal includes a dithered clock divider which has a first input adapted to receive the primary clock signal and a second input adapted to receive a random division ratio. The dithered clock divider provides a dithered clock signal. The system includes a multi-phase clock generator which has a first input adapted to receive the primary clock signal, a second input adapted to receive the dithered clock signal, and a third input adapted to receive a pseudo-random pattern. The multi-phase clock generator provides the secondary clock signals from multiple phases of the dithered clock signal. The system includes a pseudo-random pattern generator which provides the pseudo-random pattern.Type: GrantFiled: September 29, 2021Date of Patent: August 23, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Aswath Vs, Sundarrajan Rangachari, Sarma Sundareswara Gunturi, Sanjay Pennam
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Publication number: 20210391944Abstract: A transmitter includes a data stream encoder layer having an output and a pattern generator having a bit pattern output. The transmitter further includes a first multiplexer having first and second inputs and a first multiplexer output. The first input is coupled to the output of the data stream encoder layer, and the second input is coupled to the bit pattern output of the pattern generator. While at least a portion of the data stream encoder layer is powered down, the pattern generator is configured to provide bit patterns on its bit pattern output, a control signal to the first multiplexer is configured to select the second input of the first multiplexer, and the first multiplexer is configured to output the bit patterns on the output of the first multiplexer.Type: ApplicationFiled: August 31, 2021Publication date: December 16, 2021Inventors: Sanjay PENNAM, Vamsi Krishna KANDALLA, Brahmendra Reddy YATHAM, Shailesh WARDHEN, Jaiganesh BALAKRISHNAN, Jawaharlal TANGUDU
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Patent number: 11139916Abstract: A transmitter includes a data stream encoder layer having an output and a pattern generator having a bit pattern output. The transmitter further includes a first multiplexer having first and second inputs and a first multiplexer output. The first input is coupled to the output of the data stream encoder layer, and the second input is coupled to the bit pattern output of the pattern generator. While at least a portion of the data stream encoder layer is powered down, the pattern generator is configured to provide bit patterns on its bit pattern output, a control signal to the first multiplexer is configured to select the second input of the first multiplexer, and the first multiplexer is configured to output the bit patterns on the output of the first multiplexer.Type: GrantFiled: July 22, 2020Date of Patent: October 5, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sanjay Pennam, Vamsi Krishna Kandalla, Brahmendra Reddy Yatham, Shailesh Wardhen, Jaiganesh Balakrishnan, Jawaharlal Tangudu
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Publication number: 20210176005Abstract: A transmitter includes a data stream encoder layer having an output and a pattern generator having a bit pattern output. The transmitter further includes a first multiplexer having first and second inputs and a first multiplexer output. The first input is coupled to the output of the data stream encoder layer, and the second input is coupled to the bit pattern output of the pattern generator. While at least a portion of the data stream encoder layer is powered down, the pattern generator is configured to provide bit patterns on its bit pattern output, a control signal to the first multiplexer is configured to select the second input of the first multiplexer, and the first multiplexer is configured to output the bit patterns on the output of the first multiplexer.Type: ApplicationFiled: July 22, 2020Publication date: June 10, 2021Inventors: Sanjay PENNAM, Vamsi Krishna KANDALLA, Brahmendra Reddy YATHAM, Shailesh WARDHEN, Jaiganesh BALAKRISHNAN, Jawaharlal TANGUDU
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Patent number: 10812091Abstract: A method for dithering a fractional clock divider includes generating a first clock enable sequence based on a seed pattern of M ones and N minus M zeros, selecting a cyclic rotation of the seed pattern after N input clock cycles, and generating a second clock enable sequence based on the cyclic rotation. A clock gate receives the input clock signal and the clock enable sequences and outputs M clock cycles for every N input clock cycles. A random number generator indicates the cyclic rotation of the seed pattern. The seed pattern can be replaced with an updated seed pattern of M ones and N minus M zeros in a different order. In some examples, the clock enable sequence is generated using a cyclic shift register containing the seed pattern and a multiplexor. In other examples, the clock enable sequence is generated using a modulo N counter and a comparator.Type: GrantFiled: April 1, 2020Date of Patent: October 20, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sundarrajan Rangachari, Sriram Murali, Sanjay Pennam
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Publication number: 20200228126Abstract: A method for dithering a fractional clock divider includes generating a first clock enable sequence based on a seed pattern of M ones and N minus M zeros, selecting a cyclic rotation of the seed pattern after N input clock cycles, and generating a second clock enable sequence based on the cyclic rotation. A clock gate receives the input clock signal and the clock enable sequences and outputs M clock cycles for every N input clock cycles. A random number generator indicates the cyclic rotation of the seed pattern. The seed pattern can be replaced with an updated seed pattern of M ones and N minus M zeros in a different order. In some examples, the clock enable sequence is generated using a cyclic shift register containing the seed pattern and a multiplexor. In other examples, the clock enable sequence is generated using a modulo N counter and a comparator.Type: ApplicationFiled: April 1, 2020Publication date: July 16, 2020Inventors: Sundarrajan RANGACHARI, Sriram MURALI, Sanjay PENNAM
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Publication number: 20200162083Abstract: A method for dithering a fractional clock divider includes generating a first clock enable sequence based on a seed pattern of M ones and N minus M zeros, selecting a cyclic rotation of the seed pattern after N input clock cycles, and generating a second clock enable sequence based on the cyclic rotation. A clock gate receives the input clock signal and the clock enable sequences and outputs M clock cycles for every N input clock cycles. A random number generator indicates the cyclic rotation of the seed pattern. The seed pattern can be replaced with an updated seed pattern of M ones and N minus M zeros in a different order. In some examples, the clock enable sequence is generated using a cyclic shift register containing the seed pattern and a multiplexor. In other examples, the clock enable sequence is generated using a modulo N counter and a comparator.Type: ApplicationFiled: February 6, 2019Publication date: May 21, 2020Inventors: Sundarrajan RANGACHARI, Sriram MURALI, Sanjay PENNAM
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Patent number: 10651863Abstract: A method for dithering a fractional clock divider includes generating a first clock enable sequence based on a seed pattern of M ones and N minus M zeros, selecting a cyclic rotation of the seed pattern after N input clock cycles, and generating a second clock enable sequence based on the cyclic rotation. A clock gate receives the input clock signal and the clock enable sequences and outputs M clock cycles for every N input clock cycles. A random number generator indicates the cyclic rotation of the seed pattern. The seed pattern can be replaced with an updated seed pattern of M ones and N minus M zeros in a different order. In some examples, the clock enable sequence is generated using a cyclic shift register containing the seed pattern and a multiplexor. In other examples, the clock enable sequence is generated using a modulo N counter and a comparator.Type: GrantFiled: February 6, 2019Date of Patent: May 12, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sundarrajan Rangachari, Sriram Murali, Sanjay Pennam