Abstract: A mobile application development device having a platform processor, a native application converter engine, and a mobile platform framework engine configured to facilitate the development and deployment of mobile applications configured to be run on different mobile operating systems from code that is developed independently and agnostic of the mobile operating system on which it will ultimately run.

Abstract: A mobile application development device having a platform processor, a native application converter engine, and a mobile platform framework engine configured to facilitate the development and deployment of mobile applications configured to be run on different mobile operating systems from code that is developed independently and agnostic of the mobile operating system on which it will ultimately run.

Abstract: A system is provided for monitoring computing server performance using an artificial intelligence-based plugin. In particular, the system may be configured to continuously aggregate computing performance metric data of a computing device in the network, such as a server. The system may analyze the performance metric data using an artificial intelligence-based process to identify the hardware and/or software layers affected by computing workloads. Based on identifying the affected layers, the system may predict the impact of future workloads on the server and, based on the predictions, generate one or more recommendations for remediating server outages or downtime which may be caused by unanticipated volumes of network traffic, system calls, and the like. In this way, the system may provide an efficient way to optimize the use of computing resources within the network environment.

Abstract: A mobile application development device having a platform processor, a native application converter engine, and a mobile platform framework engine configured to facilitate the development and deployment of mobile applications configured to be run on different mobile operating systems from code that is developed independently and agnostic of the mobile operating system on which it will ultimately run.

Abstract: A mobile application development device having a platform processor, a native application converter engine, and a mobile platform framework engine configured to facilitate the development and deployment of mobile applications configured to be run on different mobile operating systems from code that is developed independently and agnostic of the mobile operating system on which it will ultimately run.

Abstract: A mobile application development device having a platform processor, a native application converter engine, and a mobile platform framework engine configured to facilitate the development and deployment of mobile applications configured to be run on different mobile operating systems from code that is developed independently and agnostic of the mobile operating system on which it will ultimately run.

Abstract: Embodiments of the present invention provide a system for creating configurational blocks used for building continuous real-time software logical sequences. The system is configured for creating a set of configurational blocks associated with building one or more real-time software logical sequences, displaying the set of configurational blocks, via a graphical user interface to a user, allowing the user to select one or more configurational blocks from the set of configuration blocks, receiving the one or more configurational blocks and one or more links associated with connection of the one or more configurational blocks from the user, via the graphical user interface, and generating a continuous real-time software logical sequence based on the one or more configurational blocks and the one or more links received from the user.

Abstract: A mobile application development device having a platform processor, a native application converter engine, and a mobile platform framework engine configured to facilitate the development and deployment of mobile applications configured to be run on different mobile operating systems from code that is developed independently and agnostic of the mobile operating system on which it will ultimately run.

Abstract: A mobile application development device having a platform processor, a native application converter engine, and a mobile platform framework engine configured to facilitate the development and deployment of mobile applications configured to be run on different mobile operating systems from code that is developed independently and agnostic of the mobile operating system on which it will ultimately run.

Abstract: A mobile application development device having a platform processor, a native application converter engine, and a mobile platform framework engine configured to facilitate the development and deployment of mobile applications configured to be run on different mobile operating systems from code that is developed independently and agnostic of the mobile operating system on which it will ultimately run.

Abstract: A mobile application development device having a platform processor, a native application converter engine, and a mobile platform framework engine configured to facilitate the development and deployment of mobile applications configured to be run on different mobile operating systems from code that is developed independently and agnostic of the mobile operating system on which it will ultimately run.

Abstract: This application discloses a computing system implementing a functional safety validation tool to simulate an integrated circuit design with a stimulus vector. The computing system can inject a fault at a first node of the simulated integrated circuit design, which prompts alarm logic to trigger indicating a detection of the injected fault. The computing system, in response to the triggering of the alarm logic, can initiate back-propagation to identify which intermediate nodes of the simulated integrated circuit design, located between the first node and the alarm logic, have fault values that prompt the alarm logic to trigger. The computing system can generate a fault coverage presentation identifying a diagnostic coverage of the alarm logic for the stimulus vector based on when the alarm logic.

Abstract: This application discloses a computing system implementing a functional safety validation tool to locate a vulnerable section of an electronic system described in a circuit design, select safety circuitry configured to monitor the vulnerable section of the electronic system, and modify the circuit design by inserting the safety circuitry and control circuitry into the circuit design. The control circuitry and the safety circuitry can detect faults in the vulnerable section of the electronic system. The functional safety validation tool can generate a logical equivalency check script for the modified circuit design, wherein a logical equivalency checking tool can be utilized to determine whether the modified circuit design is logically equivalent to the circuit design. The functional safety validation tool can generate a test bench for the modified circuit design, wherein at least one verification tool can be utilized in a verification environment to simulate the modified circuit design.

Abstract: A computing system implementing a functional safety validation tool to simulate a circuit design having a digital portion and an analog portion, and inject a fault into the digital portion of a simulated circuit design, which propagates towards alarm logic configured to detect the injected fault. When the injected fault propagates to a boundary between the digital portion and the analog portion, the functional safety validation tool can perform a parallel simulation of the analog portion, which propagates the injected fault from the boundary through the analog portion to an output. The functional safety validation tool can determine whether the analog portion of the circuit design suppresses the injected fault based on a value at the output. The functional safety validation tool can generate a fault coverage presentation identifying a diagnostic coverage of the alarm logic based on whether the injected fault was suppressed.

Abstract: A method is provided for analyzing failure rates due to soft/hard errors in the design of a digital electronic device. The method includes creating an error injection point by introducing a fault into a code path having a plurality of levels; determining an error detection point at which the introduced fault becomes detectable; creating a list of all of the logic cells forming the cone of logic that forms the data input to the error detection point, thereby generating a first logic cone list; creating a list of all of the logic cells forming the cone of logic that forms the data input to the error injection point, thereby generating a second logic cone list; determining the intersection between the first and second logic cone lists; and conducting a failure rate analysis on the intersection between the first and second logic cone lists.

Abstract: Low power very large scale integrated (VLSI) designs using a circuit failure in sequential cells as low voltage check for limit of operation of a design are provided. One such method involves the adding a plurality of bits for sequential elements in the design including sets of flip-flops, RAMs, ROMs and register files to add parity or single error correct and double error detect mechanism, a method to detect the parity errors or a single bit error and a double bit error in the sequential elements, starting at a voltage of operation at a nominal value and gradually lowering voltage setting till a first error is detected in the sequential elements, increasing the voltage of operation by predetermined step above a voltage of first fail to achieve an optimal voltage setting of a correct operation of the design, storing this optimal voltage setting in anon-volatile memory for a subsequent use.

Abstract: This application discloses a computing system implementing a functional safety validation tool to locate a vulnerable section of an electronic system described in a circuit design, select safety circuitry configured to monitor the vulnerable section of the electronic system, and modify the circuit design by inserting the safety circuitry and control circuitry into the circuit design. The control circuitry and the security circuitry can detect faults in the vulnerable section of the electronic system. The functional safety validation tool can generate a logical equivalency check script for the modified circuit design, which a logical equivalency checking tool can utilize to determine whether the modified circuit design is logically equivalent to the circuit design. The functional safety validation tool can generate a test bench for the modified circuit design, which at least one verification tool can utilize in a verification environment to simulate the modified circuit design.

Abstract: This application discloses a computing system implementing a functional safety validation tool to simulate a circuit design having a digital portion and an analog portion, and inject a fault into the digital portion of a simulated circuit design, which propagates towards alarm logic configured to detect the injected fault. When the injected fault propagates to a boundary between the digital portion and the analog portion, the functional safety validation tool can perform a parallel simulation of the analog portion, which propagates the injected fault from the boundary through the analog portion to an output. The functional safety validation tool can determine whether the analog portion of the circuit design suppresses the injected fault based on a value at the output. The functional safety validation tool can generate a fault coverage presentation identifying a diagnostic coverage of the alarm logic based on whether the injected fault was suppressed.

Abstract: This application discloses a computing system implementing a functional safety validation tool to simulate an integrated circuit design with a stimulus vector. The computing system can inject a fault at a first node of the simulated integrated circuit design, which prompts alarm logic to trigger indicating a detection of the injected fault. The computing system, in response to the triggering of the alarm logic, can initiate back-propagation to identify which intermediate nodes of the simulated integrated circuit design, located between the first node and the alarm logic, have fault values that prompt the alarm logic to trigger. The computing system can generate a fault coverage presentation identifying a diagnostic coverage of the alarm logic for the stimulus vector based on when the alarm logic.

Abstract: A method is provided for analyzing failure rates due to soft/hard errors in the design of a digital electronic device. The method includes creating an error injection point by introducing a fault into a code path having a plurality of levels; determining an error detection point at which the introduced fault becomes detectable; creating a list of all of the logic cells forming the cone of logic that forms the data input to the error detection point, thereby generating a first logic cone list; creating a list of all of the logic cells forming the cone of logic that forms the data input to the error injection point, thereby generating a second logic cone list; determining the intersection between the first and second logic cone lists; and conducting a failure rate analysis on the intersection between the first and second logic cone lists.