Patents by Inventor Sanjay R. Ravi

Sanjay R. Ravi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method, apparatus, and system for measurement of noise statistics and bit error ratio estimation
    Patent number: 9374202
    Abstract: A sample voltage is received from a device at a first slicer element and a second slicer element. A decision by the first slicer element based on the sample voltage is identified and compared with a decision of the second slicer element based on the sample voltage. The decision of the second slicer element is to be generated from a comparison of the sample voltage with a reference voltage for the second slicer element. Comparing the decisions can be the basis of a soft error ratio determined for a device.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: June 21, 2016
    Assignee: Intel Corporation
    Inventors: Adee O. Ran, Amir Mezer, Ophir Gazinski, Sanjay R. Ravi, David G. Ellis, Stephen J. Peters, Jeffrey M. Shuey
  • Method, apparatus and system for performing voltage margining
    Patent number: 9317353
    Abstract: In one embodiment, a receiver is coupled to a transmitter via an interconnect. The receiver includes a voltage margining circuit to receive non-deterministic data transmitted by the transmitter via a multi-level signaling scheme and to generate a bit error report including bit error information obtained at a plurality of margining levels. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 26, 2013
    Date of Patent: April 19, 2016
    Assignee: Intel Corporation
    Inventor: Sanjay R. Ravi
  • METHOD, APPARATUS AND SYSTEM FOR PERFORMING VOLTAGE MARGINING
    Publication number: 20150186197
    Abstract: In one embodiment, a receiver is coupled to a transmitter via an interconnect. The receiver includes a voltage margining circuit to receive non-deterministic data transmitted by the transmitter via a multi-level signaling scheme and to generate a bit error report including bit error information obtained at a plurality of margining levels. Other embodiments are described and claimed.
    Type: Application
    Filed: December 26, 2013
    Publication date: July 2, 2015
    Inventor: Sanjay R. Ravi
  • METHOD, APPARATUS, AND SYSTEM FOR MEASUREMENT OF NOISE STATISTICS AND BIT ERROR RATIO ESTIMATION
    Publication number: 20140281763
    Abstract: A sample voltage is received from a device at a first slicer element and a second slicer element. A decision by the first slicer element based on the sample voltage is identified and compared with a decision of the second slicer element based on the sample voltage. The decision of the second slicer element is to be generated from a comparison of the sample voltage with a reference voltage for the second slicer element. Comparing the decisions can be the basis of a soft error ration determined for a device.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Inventors: Adee O. Ran, Amir Mezer, Ophir Gazinski, Sanjay R. Ravi, David G. Ellis, Stephen J. Peters, Jeffrey M. Shuey