Abstract: Systems and methods for predicting the compressibility of data in a flash storage device are provided. One such method involves extracting byte intervals from the block of data, each of the byte intervals consisting of a preselected number of bytes, performing a hash function to map the byte intervals into a plurality of bins, the plurality of bins comprising one bin for each possible value of the byte intervals, incrementing a hit count each time more than one of the byte intervals is mapped into a single bin of the plurality of bins, and determining whether to compress the block of data based on a comparison of a ratio of the hit count to a total number of the byte intervals and a preselected threshold. This method may be implemented in hardware to ensure fast and efficient execution.

Abstract: Systems and methods for predicting the compressibility of data in a flash storage device are provided. One such method involves extracting byte intervals from the block of data, each of the byte intervals consisting of a preselected number of bytes, performing a hash function to map the byte intervals into a plurality of bins, the plurality of bins comprising one bin for each possible value of the byte intervals, incrementing a hit count each time more than one of the byte intervals is mapped into a single bin of the plurality of bins, and determining whether to compress the block of data based on a comparison of a ratio of the hit count to a total number of the byte intervals and a preselected threshold. This method may be implemented in hardware to ensure fast and efficient execution.

Abstract: Systems and methods for predicting the compressibility of data in a flash storage device are provided. One such method involves extracting byte intervals from the block of data, each of the byte intervals consisting of a preselected number of bytes, performing a hash function to map the byte intervals into a plurality of bins, the plurality of bins comprising one bin for each possible value of the byte intervals, incrementing a hit count each time more than one of the byte intervals is mapped into a single bin of the plurality of bins, and determining whether to compress the block of data based on a comparison of a ratio of the hit count to a total number of the byte intervals and a preselected threshold. This method may be implemented in hardware to ensure fast and efficient execution.

Abstract: Systems and methods for predicting the compressibility of data in a flash storage device are provided. One such method involves extracting byte intervals from the block of data, each of the byte intervals consisting of a preselected number of bytes, performing a hash function to map the byte intervals into a plurality of bins, the plurality of bins comprising one bin for each possible value of the byte intervals, incrementing a hit count each time more than one of the byte intervals is mapped into a single bin of the plurality of bins, and determining whether to compress the block of data based on a comparison of a ratio of the hit count to a total number of the byte intervals and a preselected threshold. This method may be implemented in hardware to ensure fast and efficient execution.

Abstract: An adaptive clock throttle 600 interfacing a clock generator 601 generating a high speed clock and a processing engine 602 operating in response to a processing clock. Adaptive clock throttle 600 generates a plurality of lower speed clocks from the high speed clock, estimates a duty cycle of the processing engine, and selectively gates one of the lower speed clocks to the processing engine as the processing clock to increase the duty cycle of the processing engine.

Abstract: A debugging subsystem for testing a system-on-a-chip includes an embedded processor and memory and includes at least one debugging subblock monitors a bus between the processor and the memory to detect selected triggering events, counts the number of triggering events detected and when the number of triggering events reaches a predetermined threshold, generates a debugging signal.

Abstract: A method of extracting a clock from a biphase encoded bit stream includes the step of detecting a stream of samples each having a sample size measured between consecutive bit phase transitions. A sample length is determined for each sample, the sample length approximating a number of least common multiples in the corresponding sample size. A preamble is detected from the sample lengths of a sequence of the samples and decoded to determine an expected logic level of the clock following a transition at an expected clock edge. The expected level of the clock is gated with the biphase encoded data to generate a control signal in advance of the opening of the time window. The control signal is then gated with the biphase encoded data to extract the clock edge after the time window has opened.

Abstract: A method of extracting a clock from a biphase encoded bit stream includes the step of detecting a stream of samples each having a sample size measured between consecutive bit phase transitions. A sample length is determined for each sample, the sample length approximating a number of least common multiples in the corresponding sample size. A preamble is detected from the sample lengths of a sequence of the samples and decoded to determine an expected logic level of the clock following a transition at an expected clock edge. The expected level of the clock is gated with the biphase encoded data to generate a control signal in advance of the opening of the time window. The control signal is then gated with the biphase encoded data to extract the clock edge after the time window has opened.

Abstract: A debugging subsystem for testing a system-on-a-chip includes an embedded processor and memory and includes at least one debugging subblock monitors a bus between the processor and the memory to detect selected triggering events, counts the number of triggering events detected and when the number of triggering events reaches a predetermined threshold, generates a debugging signal.