Abstract: In a flash EEPROM memory array in which a plurality of floating gate field effect transistor memory devices are arranged in rows and columns, in which wordlines are utilized to select rows of such devices and bitlines are utilized to select columns of such devices, in which groups of such devices are arranged in blocks which are independently erasable, and the blocks are divided into sub-blocks for storing lower and upper bytes of words to be stored, apparatus is provided for disabling the wordlines to all high byte sub-blocks when a low byte sub-block is to be programmed, for disabling the wordlines to all low byte sub-blocks when a high byte sub-block is to be programmed, for grounding the sources of all high byte sub-blocks when a low byte sub-block is to be programmed, and for grounding the sources of all low byte sub-blocks when a high byte sub-block is to be programmed.

Abstract: A nonvolatile memory includes a first block and a second block. The first block comprises a first memory cell and a first source line coupled to a source of the first memory cell. The second block comprises a second memory cell and a second source line coupled to a source of the second memory cell. A first source switch is coupled to the first source line for selectively coupling a first potential, a second potential, and a third potential to the first source line. The second potential has a voltage intermediate between the first potential and the third potential. A second source switch is coupled to the second source line for selectively coupling one of the first, second, and third potentials to the second source line. A block select circuit receives a block address for selecting one of the first and second source switches to couple one of the first, second, and third potentials to its respective one of the first and second source lines.

Abstract: A nonvolatile memory device residing on a substrate is described. The memory device includes a first block and a second block. The first block includes a first sub-block comprising a first memory cell, a first bit line coupled to a drain of the first memory cell, and a first source line coupled to a source of the first memory cell. The first block also includes a second sub-block which includes a second memory cell, a second bit line coupled to a drain of the second memory cell, and a second source line coupled to a source of the second memory cell. The second block comprises a third sub-block comprising a third memory cell, a third bit line coupled to a drain of the third memory cell, and a third source line coupled to a source of the third memory cell. The second block also includes a fourth sub-block which includes a fourth memory cell, a fourth bit line coupled to a drain of the fourth memory cell, and a fourth source line coupled to a source of the fourth memory cell.