Abstract: A component and a system for mitigating coke formation during delivery of a hydrocarbon fluid. The component includes a contact surface configured to be in contact with the hydrocarbon fluid. Tuning the zeta potential of the contact surface allows selective attraction and/or repulsion of coke-catalyzing materials, metal ions, heteroatomic hydrocarbons, and/or coke precursors present in the hydrocarbon fluid. A method of mitigating coke formation during delivery of a hydrocarbon fluid includes tuning a zeta potential of the contact surface of the component and injecting or circulating the hydrocarbon fluid through the system such that the contact surface selectively attracts and/or repels coke-catalyzing materials, metal ions, heteroatomic hydrocarbons, and/or coke precursors present in the hydrocarbon fluid.

Abstract: The invention relates to a method of treating or preventing Parkinson's disease in a subject comprising administering a compound of Formula I wherein, R1 is —NHC(O) C3-6 cycloalkyl and R2 is hydrogen; or R1 and R2 along with the carbon atoms to which they are attached form a six membered aromatic ring, wherein the ring is substituted with one or more groups selected from hydrogen, halogen and C1-6 alkyl; R3 and R4 are independently selected from group comprising hydrogen, halogen, C1-3 alkyl, OC1-3 alkyl, NO2, SC1-3 alkyl, C1-3 haloalkyl, OC1-3 haloalkyl, and SC1-3 haloalkyl; or a pharmaceutically acceptable salt thereof.

Abstract: The present disclosure provides a system for generating cyber threat intelligence. The system includes a plurality of honeynets configured to emulate one or more services; a plurality of sensors, each sensor associated with a honeynet, each sensor configured to detect cyberattacks on the associated honeynet; a data collector configured to receive data relating to the cyberattacks on the plurality of honeynets; and a computing device configured to detect, from the sensors, one or more cyberattacks on the honeynets based on analysis of network traffic through the honeynets; extract, from detected cyberattacks on the honeynets, a detailed forensic data log based on analysis of content of the data packets pertaining to the cyberattacks on the honeynets; and transmit the detailed forensic data log to the data collector. The data collector stores the detailed forensic data log for further analysis in order to generate cyber threat intelligence.

Abstract: A packaged component includes a pattern generator for generating successive random data patterns. The component further includes a programmable constraint correction module, coupled to the pattern generator, to replace undesirable random data patterns with desirable bit sequences to overcome bus contention problems in the generated random data patterns. The component further includes an integrated circuit device to be functionally tested. The device receives the constrained random data patterns from the constraint correction module and outputs a test result. The device further includes a programmable X-masking module coupled to the device receives and masks the test result by replacing unpredictable bit values in the received test result with predictable bit values. A signature analyzer coupled to the X-masking module receives the masked test result and compresses the test result into a signature.

Abstract: A generalized fault model. For one aspect, extracted faults may be modeled using a fault model in which at least one of the following is specified: multiple fault atoms, two or more impact conditions for a first set of excitation conditions, a relative priority of fault atoms within a set of fault atoms used to model the at least one extracted fault, a dynamic fault delay, and excitation conditions including at least a first mandatory excitation condition and at least a second optional excitation condition.

Abstract: A generalized fault model. For one aspect, extracted faults may be modeled using a fault model in which at least one of the following is specified: multiple fault atoms, two or more impact conditions for a first set of excitation conditions, a relative priority of fault atoms within a set of fault atoms used to model the at least one extracted fault, a dynamic fault duration, and excitation conditions including at least a first mandatory excitation condition and at least a second optional excitation condition.

Abstract: A generalized fault model. For one aspect, extracted faults may be modeled using a fault model in which at least one of the following is specified: multiple fault atoms, two or more impact conditions for a first set of excitation conditions, a relative priority of fault atoms within a set of fault atoms used to model the at least one extracted fault, a dynamic fault delay, and excitation conditions including at least a first mandatory excitation condition and at least a second optional excitation condition.

Abstract: A packaged component includes a pattern generator for generating successive random data patterns. The component further includes a programmable constraint correction module, coupled to the pattern generator, to replace undesirable random data patterns with desirable bit sequences to overcome bus contention problems in the generated random data patterns. The component further includes an integrated circuit device to be functionally tested. The device receives the constrained random data patterns from the constraint correction module and outputs a test result. The device further includes a programmable X-masking module coupled to the device receives and masks the test result by replacing unpredictable bit values in the received test result with predictable bit values. A signature analyzer coupled to the X-masking module receives the masked test result and compresses the test result into a signature.

Abstract: A test system for structurally testing an integrated circuit device includes a pattern generator for generating successive random data patterns (scan chain). The test system further includes a constraint checker and corrector module, coupled to the pattern generator, to replace undesirable random data patterns (state elements joined together in the scan chain such that one state element is connected to a ground and the other state element is connected to a power supply) with desirable bit sequences to eliminate bus contention problems in the generated random data patterns. The test system further includes the integrated circuit device to be tested. The integrated circuit device receives the constrained random data patterns from the constraint checker and corrector module and outputs a test result. The test system further includes an X-masking module coupled to the integrated circuit device.

Abstract: A technique for a scan design employing a register transfer level scan selection which requires that either all bits of a register are designated to have all scan or all non-scan properties. No separate elements (bits) of a register are selected for individual scan. By designating scan selection at the register level, register-transfer-level (RTL) specifications of a digital circuit can employ signal flow vectors at the register level and not at the conventional logic gate level. In one technique, a number of registers are grouped to have the same scan or non-scan property. Such grouping is used to provide a common template for inserting scan into multiple instantiated modules. The group designation for selecting scan or non-scan registers is also used to scan registers at the memory input, output, both input and output, or neither, which then can be used for testing memory devices.