Patents by Inventor Sanjay Sunder

Sanjay Sunder has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11917475
    Abstract: Methods and mechanisms for performing idle mode mobility procedures are provided. According to one aspect of the present disclosure, a method for wireless communication performed by a user equipment (UE) includes: receiving, from a base station (BS) on a first cell, system information indicating a first cell reselection priority configuration; receiving, from the BS, dedicated signaling indicating a dedicated cell reselection priority configuration, wherein the dedicated cell reselection priority configuration is empty; and connecting, while in an idle mode and in response to the dedicated cell reselection priority configuration being empty, to a second cell different from the first cell based on the first cell reselection priority configuration received in the system information.
    Type: Grant
    Filed: December 1, 2021
    Date of Patent: February 27, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Sanjay Kumar, Uttam Vyas, Muralidharan Murugan, Sham Sunder Kantayapalem
  • Publication number: 20240019485
    Abstract: Techniques for testing connectivity between a first integrated circuit (IC) and a second IC of an electronics package are described. An example technique involves controlling a switch(es) in the first IC to configure a bias direction of a photodiode of the second IC to forward biased. A connectivity test between the first and second ICs is performed, when the photodiode is forward biased. Another technique involves controlling a switch(es) in the first IC to configure a bias direction of a photodiode in the second IC to reverse biased. A first voltage is measured at an input of a transimpedance amplifier (TIA) in the first IC when the photodiode is reverse biased. The switch(es) are controlled to change the bias direction of the photodiode to forward biased. A second voltage is measured at the input of the TIA when the photodiode is forward biased.
    Type: Application
    Filed: July 18, 2022
    Publication date: January 18, 2024
    Inventors: Sanjay SUNDER, Alexander C. KURYLAK
  • Patent number: 11639955
    Abstract: The fault detection system described provides an efficient method to test and monitor component to component connectivity in an electronic package using on chip test circuits and on chip components, which reduces the need for external testing equipment and analysis. The on chip nature allows for both real time testing in the assembly process of the electronic packages and during use of the electronic package by determining an on chip reference measurement and using the reference measurement to determine an operational status of the package.
    Type: Grant
    Filed: August 23, 2021
    Date of Patent: May 2, 2023
    Assignee: Cisco Technology, Inc.
    Inventors: Sanjay Sunder, Prajwal M. Kasturi, Joseph V. Pampanin, Craig S. Appel
  • Publication number: 20230100245
    Abstract: An integrated circuit includes a transimpedance amplifier and an injection circuit. The injection circuit generates a first electrical test signal and injects the first electrical test signal into the transimpedance amplifier. The first electrical test signal or an output of the transimpedance amplifier generated based on the first electrical test signal is used to determine whether the integrated circuit is faulty.
    Type: Application
    Filed: September 24, 2021
    Publication date: March 30, 2023
    Inventors: Sanjay SUNDER, Alexander C. KURYLAK, Kadaba LAKSHMIKUMAR
  • Publication number: 20220337194
    Abstract: Embodiments provide for a tunable driving circuit by monitoring a frequency of a ring oscillator of an electrical integrated circuit connected to an optical modulator to determine operational characteristics of the electrical integrated circuit; setting, based on the operational characteristics, a driving voltage for a plurality of tunable inverters and a plurality of fixed gain inverters that control the optical modulator, wherein each tunable inverter of the plurality of tunable inverters is connected in parallel with a corresponding fixed gain inverter of the plurality of fixed gain inverters on one of a first arm and a second arm connected to the optical modulator; and setting an amplification strength for the plurality of tunable inverters based on the operational characteristics.
    Type: Application
    Filed: July 5, 2022
    Publication date: October 20, 2022
    Inventors: Craig S. APPEL, Peter C. METZ, Joseph V. PAMPANIN, Sanjay SUNDER
  • Patent number: 11411538
    Abstract: Embodiments provide for a tunable driving circuit by monitoring a frequency of a ring oscillator of an electrical integrated circuit connected to an optical modulator to determine operational characteristics of the electrical integrated circuit; setting, based on the operational characteristics, a driving voltage for a plurality of tunable inverters and a plurality of fixed gain inverters that control the optical modulator, wherein each tunable inverter of the plurality of tunable inverters is connected in parallel with a corresponding fixed gain inverter of the plurality of fixed gain inverters on one of a first arm and a second arm connected to the optical modulator; and setting an amplification strength for the plurality of tunable inverters based on the operational characteristics.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: August 9, 2022
    Assignee: Cisco Technology, Inc.
    Inventors: Craig S. Appel, Peter C. Metz, Joseph V. Pampanin, Sanjay Sunder
  • Publication number: 20210382106
    Abstract: The fault detection system described provides an efficient method to test and monitor component to component connectivity in an electronic package using on chip test circuits and on chip components, which reduces the need for external testing equipment and analysis. The on chip nature allows for both real time testing in the assembly process of the electronic packages and during use of the electronic package by determining an on chip reference measurement and using the reference measurement to determine an operational status of the package.
    Type: Application
    Filed: August 23, 2021
    Publication date: December 9, 2021
    Inventors: Sanjay SUNDER, Prajwal M. KASTURI, Joseph V. PAMPANIN, Craig S. APPEL
  • Patent number: 11099229
    Abstract: The fault detection system described provides an efficient method to test and monitor component to component connectivity in an electronic package using on chip test circuits and on chip components, which reduces the need for external testing equipment and analysis. The on chip nature allows for both real time testing in the assembly process of the electronic packages and during use of the electronic package by determining an on chip reference measurement and using the reference measurement to determine an operational status of the package.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: August 24, 2021
    Assignee: Cisco Technology, Inc.
    Inventors: Sanjay Sunder, Prajwal M. Kasturi, Joseph V. Pampanin, Craig S. Appel
  • Publication number: 20210215754
    Abstract: The fault detection system described provides an efficient method to test and monitor component to component connectivity in an electronic package using on chip test circuits and on chip components, which reduces the need for external testing equipment and analysis. The on chip nature allows for both real time testing in the assembly process of the electronic packages and during use of the electronic package by determining an on chip reference measurement and using the reference measurement to determine an operational status of the package.
    Type: Application
    Filed: January 10, 2020
    Publication date: July 15, 2021
    Applicants: Cisco Technology, Inc., Cisco Technology, Inc.
    Inventors: Sanjay Sunder, Prajwal M. Kasturi, Joseph V. Pampanin, Craig S. Appel
  • Patent number: 10965377
    Abstract: Thermal tuning and quadrature control of opto-electronic devices using active extinction ratio tracking is proved by phase shifting, via a first phase shifter, a first optical signal carried on a first arm of an interferometer relative to a second optical signal carried on a second arm of the interferometer; combining the first optical signal with the second optical signal as an output signal; detecting a peak value in the output signal; and adjusting a relative phase offset imparted by the first phase shifter on the first optical signal relative to the second optical signal, based on the peak value, to increase an amplitude of the peak value. In various embodiments, the peak value is increased over time to maximize an extinction ratio of the optoelectronic device and maintain the extinction ratio in a maximized state during operation.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: March 30, 2021
    Assignee: Cisco Technology, Inc.
    Inventors: Craig S. Appel, Romesh Kumar Nandwana, Sanjay Sunder, Kadaba Lakshmikumar
  • Patent number: 10880014
    Abstract: Active relative intensity noise mitigation in nested interferometers using trans-impedance amplifiers is provided by splitting an optical carrier signal into a first version and a second version, wherein the first version is orthogonal to the second version; re-combining predefined portions of the first version and the second version to determine a noise level; modulating at least one of the first version and the second version based on the noise level to reduce the noise level; after modulating the at least one of the first version and the second version based on the noise level, encoding data onto at least one of the first version and the second version; and recombining the first version and the second version to transmit the data.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: December 29, 2020
    Assignee: Cisco Technology, Inc.
    Inventors: Sanjay Sunder, Romesh Kumar Nandwana, Craig S. Appel
  • Publication number: 20200373885
    Abstract: Embodiments provide for a tunable driving circuit by monitoring a frequency of a ring oscillator of an electrical integrated circuit connected to an optical modulator to determine operational characteristics of the electrical integrated circuit; setting, based on the operational characteristics, a driving voltage for a plurality of tunable inverters and a plurality of fixed gain inverters that control the optical modulator, wherein each tunable inverter of the plurality of tunable inverters is connected in parallel with a corresponding fixed gain inverter of the plurality of fixed gain inverters on one of a first arm and a second arm connected to the optical modulator; and setting an amplification strength for the plurality of tunable inverters based on the operational characteristics.
    Type: Application
    Filed: May 20, 2019
    Publication date: November 26, 2020
    Inventors: Craig S. APPEL, Peter C. METZ, Joseph V. PAMPANIN, Sanjay SUNDER
  • Patent number: 5936894
    Abstract: The present invention concerns a method and apparatus for providing a dual level wordline clamp for use in a memory array. During a write operation, the clamp is at a level that ensures that a proper write margin is maintained. During a read operation, the clamp produces a lower level that reduces the overall current consumption of the circuit. During a write operation, the clamp also reduces the overall current consumption of the circuit. The present invention does not require complex reference circuits and, as a result, presents a minimal impact on die size.
    Type: Grant
    Filed: June 15, 1998
    Date of Patent: August 10, 1999
    Assignee: Cypress Semiconductor Corp.
    Inventors: Andrew L. Hawkins, Jeffery Scott Hunt, Satish C. Saripella, Sanjay Sunder
  • Patent number: 5864507
    Abstract: The present invention concerns a method and apparatus for providing a dual level wordline clamp for use in a memory array. During a write operation, the clamp is at a level that ensures that a proper write margin is maintained. During a read operation, the clamp produces a lower level that reduces the overall current consumption of the circuit. During a write operation, the clamp also reduces the overall current consumption of the circuit. The present invention does not require complex reference circuits and, as a result, presents a minimal impact on die size.
    Type: Grant
    Filed: December 18, 1996
    Date of Patent: January 26, 1999
    Assignee: Cypress Semiconductor Corporation
    Inventors: Andrew L. Hawkins, Jeffery Scott Hunt, Satish C. Saripella, Sanjay Sunder