Patents by Inventor Sanjay Sunder
Sanjay Sunder has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12537604Abstract: Provided herein are techniques to facilitate automatic gain control for an optical receiver. In one example, a method may include for a first mode, first adjusting, for a received optical input signal, at least one of: a coarse gain of a programmable gain amplifier (PGA), a fine gain of the PGA, or an attenuation of a variable optical attenuator (VOA) until a voltage swing peak value of an output signal of the optical receiver satisfies a first voltage swing peak range. The method may further include, through a second mode, triggering second adjusting of at least one of the VOA attenuation or the PGA fine gain based on determining that the voltage swing peak value of the output signal does not satisfy a second voltage swing peak range or that another voltage swing peak value obtained from an external signal processing device does not satisfy another voltage swing peak range.Type: GrantFiled: November 28, 2023Date of Patent: January 27, 2026Assignee: CISCO TECHNOLOGY, INC.Inventors: Alexander C. Kurylak, Sanjay Sunder, Pratiksh Parikh, Jenjen Tiao, Bibhu P. Das, Kadaba Lakshmikumar
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Patent number: 12487275Abstract: Techniques for testing connectivity between a first integrated circuit (IC) and a second IC of an electronics package are described. An example technique involves controlling a switch(es) in the first IC to configure a bias direction of a photodiode of the second IC to forward biased. A connectivity test between the first and second ICs is performed, when the photodiode is forward biased. Another technique involves controlling a switch(es) in the first IC to configure a bias direction of a photodiode in the second IC to reverse biased. A first voltage is measured at an input of a transimpedance amplifier (TIA) in the first IC when the photodiode is reverse biased. The switch(es) are controlled to change the bias direction of the photodiode to forward biased. A second voltage is measured at the input of the TIA when the photodiode is forward biased.Type: GrantFiled: April 30, 2024Date of Patent: December 2, 2025Assignee: Cisco Technology, Inc.Inventors: Sanjay Sunder, Alexander C. Kurylak
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Publication number: 20250294271Abstract: Lane drop detection techniques for multi-lane optical transceivers are provided. In one aspect, a method includes capturing a phase interpolator (PI) control word for each lane of an optical transceiver; determining a lane difference between a master lane and each non-master lane; calculating a difference associated with each non-master lane, wherein the difference associated with a given non-master lane is calculated as a difference between the lane difference associated with the given non-master lane and a reference lane difference associated with the given non-master lane; upon determining that at least one of the differences has reached a drift threshold, determining that the master lane or one or more of the non-master lanes is invalid based on which of the differences have reached the drift threshold; and performing a control action when the master lane or one or more of the non-master lanes is invalid.Type: ApplicationFiled: March 17, 2025Publication date: September 18, 2025Inventors: Romesh Kumar NANDWANA, Abhishek BHAT, Jenjen TIAO, Sai Suhas ARRA, Sanjay SUNDER
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Publication number: 20250293783Abstract: Frequency error tracking and lane monitoring techniques for multi-lane optical transceivers are provided. In one aspect, a method includes capturing phase and frequency information recovered by clock-and-data recovery circuits from data traveling along a plurality of lanes of an optical transceiver, with one of the lanes being a master lane; determining a frequency error based on the phase and frequency information of the master lane; outputting, by a tunable oscillator, a reference clock based on the frequency error; and controlling the optical transceiver based on i) a transmitter clock signal generated by a transmitter phase-locked loop (PLL) using the reference clock signal, and ii) a receiver clock signal generated by a receiver PLL using the reference clock signal.Type: ApplicationFiled: March 13, 2025Publication date: September 18, 2025Inventors: Abhishek BHAT, Jenjen TIAO, Sai Suhas ARRA, Romesh Kumar NANDWANA, Sanjay SUNDER
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Publication number: 20250175257Abstract: Provided herein are techniques to facilitate automatic gain control for an optical receiver. In one example, a method may include for a first mode, first adjusting, for a received optical input signal, at least one of: a coarse gain of a programmable gain amplifier (PGA), a fine gain of the PGA, or an attenuation of a variable optical attenuator (VOA) until a voltage swing peak value of an output signal of the optical receiver satisfies a first voltage swing peak range. The method may further include, through a second mode, triggering second adjusting of at least one of the VOA attenuation or the PGA fine gain based on determining that the voltage swing peak value of the output signal does not satisfy a second voltage swing peak range or that another voltage swing peak value obtained from an external signal processing device does not satisfy another voltage swing peak range.Type: ApplicationFiled: November 28, 2023Publication date: May 29, 2025Inventors: Alexander C. Kurylak, Sanjay Sunder, Pratiksh Parikh, Jenjen Tiao, Bibhu P. Das, Kadaba Lakshmikumar
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Publication number: 20240421772Abstract: Embodiments provide for a tunable driving circuit by monitoring a frequency of a ring oscillator of an electrical integrated circuit connected to an optical modulator to determine operational characteristics of the electrical integrated circuit; setting, based on the operational characteristics, a driving voltage for a plurality of tunable inverters and a plurality of fixed gain inverters that control the optical modulator, wherein each tunable inverter of the plurality of tunable inverters is connected in parallel with a corresponding fixed gain inverter of the plurality of fixed gain inverters on one of a first arm and a second arm connected to the optical modulator; and setting an amplification strength for the plurality of tunable inverters based on the operational characteristics.Type: ApplicationFiled: August 23, 2024Publication date: December 19, 2024Inventors: Craig S. APPEL, Peter C. METZ, Joseph V. PAMPANIN, Sanjay SUNDER
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Patent number: 12107556Abstract: An integrated circuit includes a transimpedance amplifier and an injection circuit. The injection circuit generates a first electrical test signal and injects the first electrical test signal into the transimpedance amplifier. The first electrical test signal or an output of the transimpedance amplifier generated based on the first electrical test signal is used to determine whether the integrated circuit is faulty.Type: GrantFiled: September 24, 2021Date of Patent: October 1, 2024Assignee: Cisco Technology, Inc.Inventors: Sanjay Sunder, Alexander C. Kurylak, Kadaba Lakshmikumar
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Patent number: 12095421Abstract: Embodiments provide for a tunable driving circuit by monitoring a frequency of a ring oscillator of an electrical integrated circuit connected to an optical modulator to determine operational characteristics of the electrical integrated circuit; setting, based on the operational characteristics, a driving voltage for a plurality of tunable inverters and a plurality of fixed gain inverters that control the optical modulator, wherein each tunable inverter of the plurality of tunable inverters is connected in parallel with a corresponding fixed gain inverter of the plurality of fixed gain inverters on one of a first arm and a second arm connected to the optical modulator; and setting an amplification strength for the plurality of tunable inverters based on the operational characteristics.Type: GrantFiled: July 5, 2022Date of Patent: September 17, 2024Assignee: Cisco Technology, Inc.Inventors: Craig S. Appel, Peter C. Metz, Joseph V. Pampanin, Sanjay Sunder
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Publication number: 20240280630Abstract: Techniques for testing connectivity between a first integrated circuit (IC) and a second IC of an electronics package are described. An example technique involves controlling a switch(es) in the first IC to configure a bias direction of a photodiode of the second IC to forward biased. A connectivity test between the first and second ICs is performed, when the photodiode is forward biased. Another technique involves controlling a switch(es) in the first IC to configure a bias direction of a photodiode in the second IC to reverse biased. A first voltage is measured at an input of a transimpedance amplifier (TIA) in the first IC when the photodiode is reverse biased. The switch(es) are controlled to change the bias direction of the photodiode to forward biased. A second voltage is measured at the input of the TIA when the photodiode is forward biased.Type: ApplicationFiled: April 30, 2024Publication date: August 22, 2024Inventors: Sanjay SUNDER, Alexander C. KURYLAK
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Patent number: 12007432Abstract: Techniques for testing connectivity between a first integrated circuit (IC) and a second IC of an electronics package are described. An example technique involves controlling a switch(es) in the first IC to configure a bias direction of a photodiode of the second IC to forward biased. A connectivity test between the first and second ICs is performed, when the photodiode is forward biased. Another technique involves controlling a switch(es) in the first IC to configure a bias direction of a photodiode in the second IC to reverse biased. A first voltage is measured at an input of a transimpedance amplifier (TIA) in the first IC when the photodiode is reverse biased. The switch(es) are controlled to change the bias direction of the photodiode to forward biased. A second voltage is measured at the input of the TIA when the photodiode is forward biased.Type: GrantFiled: July 18, 2022Date of Patent: June 11, 2024Assignee: Cisco Technology, Inc.Inventors: Sanjay Sunder, Alexander C. Kurylak
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Publication number: 20240019485Abstract: Techniques for testing connectivity between a first integrated circuit (IC) and a second IC of an electronics package are described. An example technique involves controlling a switch(es) in the first IC to configure a bias direction of a photodiode of the second IC to forward biased. A connectivity test between the first and second ICs is performed, when the photodiode is forward biased. Another technique involves controlling a switch(es) in the first IC to configure a bias direction of a photodiode in the second IC to reverse biased. A first voltage is measured at an input of a transimpedance amplifier (TIA) in the first IC when the photodiode is reverse biased. The switch(es) are controlled to change the bias direction of the photodiode to forward biased. A second voltage is measured at the input of the TIA when the photodiode is forward biased.Type: ApplicationFiled: July 18, 2022Publication date: January 18, 2024Inventors: Sanjay SUNDER, Alexander C. KURYLAK
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Patent number: 11639955Abstract: The fault detection system described provides an efficient method to test and monitor component to component connectivity in an electronic package using on chip test circuits and on chip components, which reduces the need for external testing equipment and analysis. The on chip nature allows for both real time testing in the assembly process of the electronic packages and during use of the electronic package by determining an on chip reference measurement and using the reference measurement to determine an operational status of the package.Type: GrantFiled: August 23, 2021Date of Patent: May 2, 2023Assignee: Cisco Technology, Inc.Inventors: Sanjay Sunder, Prajwal M. Kasturi, Joseph V. Pampanin, Craig S. Appel
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Publication number: 20230100245Abstract: An integrated circuit includes a transimpedance amplifier and an injection circuit. The injection circuit generates a first electrical test signal and injects the first electrical test signal into the transimpedance amplifier. The first electrical test signal or an output of the transimpedance amplifier generated based on the first electrical test signal is used to determine whether the integrated circuit is faulty.Type: ApplicationFiled: September 24, 2021Publication date: March 30, 2023Inventors: Sanjay SUNDER, Alexander C. KURYLAK, Kadaba LAKSHMIKUMAR
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Publication number: 20220337194Abstract: Embodiments provide for a tunable driving circuit by monitoring a frequency of a ring oscillator of an electrical integrated circuit connected to an optical modulator to determine operational characteristics of the electrical integrated circuit; setting, based on the operational characteristics, a driving voltage for a plurality of tunable inverters and a plurality of fixed gain inverters that control the optical modulator, wherein each tunable inverter of the plurality of tunable inverters is connected in parallel with a corresponding fixed gain inverter of the plurality of fixed gain inverters on one of a first arm and a second arm connected to the optical modulator; and setting an amplification strength for the plurality of tunable inverters based on the operational characteristics.Type: ApplicationFiled: July 5, 2022Publication date: October 20, 2022Inventors: Craig S. APPEL, Peter C. METZ, Joseph V. PAMPANIN, Sanjay SUNDER
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Patent number: 11411538Abstract: Embodiments provide for a tunable driving circuit by monitoring a frequency of a ring oscillator of an electrical integrated circuit connected to an optical modulator to determine operational characteristics of the electrical integrated circuit; setting, based on the operational characteristics, a driving voltage for a plurality of tunable inverters and a plurality of fixed gain inverters that control the optical modulator, wherein each tunable inverter of the plurality of tunable inverters is connected in parallel with a corresponding fixed gain inverter of the plurality of fixed gain inverters on one of a first arm and a second arm connected to the optical modulator; and setting an amplification strength for the plurality of tunable inverters based on the operational characteristics.Type: GrantFiled: May 20, 2019Date of Patent: August 9, 2022Assignee: Cisco Technology, Inc.Inventors: Craig S. Appel, Peter C. Metz, Joseph V. Pampanin, Sanjay Sunder
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Publication number: 20210382106Abstract: The fault detection system described provides an efficient method to test and monitor component to component connectivity in an electronic package using on chip test circuits and on chip components, which reduces the need for external testing equipment and analysis. The on chip nature allows for both real time testing in the assembly process of the electronic packages and during use of the electronic package by determining an on chip reference measurement and using the reference measurement to determine an operational status of the package.Type: ApplicationFiled: August 23, 2021Publication date: December 9, 2021Inventors: Sanjay SUNDER, Prajwal M. KASTURI, Joseph V. PAMPANIN, Craig S. APPEL
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Patent number: 11099229Abstract: The fault detection system described provides an efficient method to test and monitor component to component connectivity in an electronic package using on chip test circuits and on chip components, which reduces the need for external testing equipment and analysis. The on chip nature allows for both real time testing in the assembly process of the electronic packages and during use of the electronic package by determining an on chip reference measurement and using the reference measurement to determine an operational status of the package.Type: GrantFiled: January 10, 2020Date of Patent: August 24, 2021Assignee: Cisco Technology, Inc.Inventors: Sanjay Sunder, Prajwal M. Kasturi, Joseph V. Pampanin, Craig S. Appel
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Publication number: 20210215754Abstract: The fault detection system described provides an efficient method to test and monitor component to component connectivity in an electronic package using on chip test circuits and on chip components, which reduces the need for external testing equipment and analysis. The on chip nature allows for both real time testing in the assembly process of the electronic packages and during use of the electronic package by determining an on chip reference measurement and using the reference measurement to determine an operational status of the package.Type: ApplicationFiled: January 10, 2020Publication date: July 15, 2021Applicants: Cisco Technology, Inc., Cisco Technology, Inc.Inventors: Sanjay Sunder, Prajwal M. Kasturi, Joseph V. Pampanin, Craig S. Appel
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Patent number: 10965377Abstract: Thermal tuning and quadrature control of opto-electronic devices using active extinction ratio tracking is proved by phase shifting, via a first phase shifter, a first optical signal carried on a first arm of an interferometer relative to a second optical signal carried on a second arm of the interferometer; combining the first optical signal with the second optical signal as an output signal; detecting a peak value in the output signal; and adjusting a relative phase offset imparted by the first phase shifter on the first optical signal relative to the second optical signal, based on the peak value, to increase an amplitude of the peak value. In various embodiments, the peak value is increased over time to maximize an extinction ratio of the optoelectronic device and maintain the extinction ratio in a maximized state during operation.Type: GrantFiled: January 16, 2020Date of Patent: March 30, 2021Assignee: Cisco Technology, Inc.Inventors: Craig S. Appel, Romesh Kumar Nandwana, Sanjay Sunder, Kadaba Lakshmikumar
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Patent number: 10880014Abstract: Active relative intensity noise mitigation in nested interferometers using trans-impedance amplifiers is provided by splitting an optical carrier signal into a first version and a second version, wherein the first version is orthogonal to the second version; re-combining predefined portions of the first version and the second version to determine a noise level; modulating at least one of the first version and the second version based on the noise level to reduce the noise level; after modulating the at least one of the first version and the second version based on the noise level, encoding data onto at least one of the first version and the second version; and recombining the first version and the second version to transmit the data.Type: GrantFiled: January 3, 2020Date of Patent: December 29, 2020Assignee: Cisco Technology, Inc.Inventors: Sanjay Sunder, Romesh Kumar Nandwana, Craig S. Appel