Abstract: Systems and methods for diagnostic visual search can include processing a search query with a plurality of classification models to determine a search query intent and predict potential diagnosis. The search query can include an image that is processed to determine the presence of a body part and may be processed to determine if the search query is descriptive of a diagnostic search query. Based on the intent determination, the image may then be processed by a conditions classification model to determine one or more predicted condition classifications. Condition information can then be obtained and provided based on the one or more predicted condition classifications.

Abstract: Apparatus and systems, as well as methods and articles, may perform operations including memory bank management and memory bus arbitration associated with a first memory module comprising non-refreshable memory cells and a controller, a second memory module coupled to the first memory module by a memory management control bus, or both. Some embodiments may also perform precharge and refresh operations associated with the second memory module.

Abstract: A method and apparatus for partitioning a flash memory device is provided. The flash memory device includes a plurality of partitions, each partition able to be read, written, or erased simultaneously with the other partitions.

Abstract: A low-power interface for nonvolatile writeable memory is described. The interface includes an input buffer and an output buffer. The input buffer receives input signals having one of a number of pairs of logic levels. The input buffer is coupled to the nonvolatile writeable memory and coupled to the same power supply as the nonvolatile writeable memory. The input buffer translates the input signals received to the signal level used by the nonvolatile writeable memory. The output buffer is coupled to the nonvolatile writeable memory and is coupled to a different power supply from the input buffer and the nonvolatile writeable memory. The output buffer translates the signals received from the nonvolatile writeable memory to the same signal levels as the input signal. The input buffer and output buffer utilize input/output signals having logic levels compatible with complementary metal-oxide semiconductor (CMOS) technology.

Abstract: A power supply lockout circuit that prevents corruption of nonvolatile writeable memory data is described. The power supply lockout circuit monitors the power supply signals from several power supplies. The power supply lockout circuit locks out commands writing to the nonvolatile writeable memory when any one of the monitored power supply signals coupled to the nonvolatile writeable memory is below a specified signal level. The power supply lockout circuit includes a detector which provides a lockout signal to the nonvolatile writeable memory when a power supply signal is less than a prespecified voltage. The power supply lockout circuit also includes a sampling circuit which provides other lockout signals to the nonvolatile writeable memory when a different power supply signal is less than a reference voltage.

Abstract: Methods and apparatus for determining the state of a memory cell having more than two possible states are disclosed. For a first embodiment, the state of a flash cell having n states, where n is a power of 2, is determined by selectively comparing the threshold voltage V.sub.t of a selected memory cell to (n-1) reference voltages. For every two states, a single comparator is provided such that the total number of comparators is equal to the number of bits stored in the memory cell.

Abstract: Methods and apparatus for determining the state of a memory cell having more than two possible states are disclosed. For a first embodiment, the state of a flash cell having n states, where n is a power of 2, is determined by selectively comparing the threshold voltage V.sub.t of a selected memory cell to (n-1) reference voltages. For every two states, a single comparator is provided such that the total number of comparators is equal to the number of bits stored in the memory cell.

Abstract: A method for verifying that a flash EEPROM memory device has reached a programmed state including the steps of providing a programming pulse of a preselected level and unspecified duration to the device, monitoring the current through the device as the programming pulse is applied, and providing a signal to terminate the programming pulse when the current through the device reaches a state equivalent to that through a programmed device.