Patents by Inventor Sanjaya Anand

Sanjaya Anand has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9588920
    Abstract: Methods and systems for sending and receiving information in a network are provided. The method includes configuring a port trunk as a PCI-Express function by an adapter, where the port trunk includes a plurality of network links that couple an adapter port to a port of another device; configuring the port of the other device for using the port trunk for sending and receiving information to and from the adapter port; transferring data by the adapter port on a same link for a write operation belonging to a same transaction for writing the data at a storage location; and receiving a confirmation for completing the write operation from the port of the other device after the data is written at the storage location, where the port of the other devices also uses a same link for sending information to the adapter port for the same transaction.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: March 7, 2017
    Assignee: QLOGIC, Corporation
    Inventors: Sanjaya Anand, Kathy K. Caballero
  • Patent number: 8793399
    Abstract: Method and System for processing network information is provided. The system includes a computing system having a processor for executing instructions for an application module that generates an input/output (“I/O”) request for transmitting and receiving network information to and from the network device; a storage driver for receiving the I/O request from the application module; a network protocol stack for executing a network protocol layer for processing network related information; and an accelerator module that interfaces with the storage driver and the network protocol stack for accelerating processing of Internet Small Computer System Interface (iSCSI) protocol data units (PDUs).
    Type: Grant
    Filed: August 5, 2009
    Date of Patent: July 29, 2014
    Assignee: QLOGIC, Corporation
    Inventors: Murali Rajagopal, Jerald K. Alston, Sanjaya Anand, Bruce A. Klemin
  • Patent number: 7676611
    Abstract: A method and system for processing out of order frames received by a host bus adapter is provided. The method includes, determining if a current frame is out of order; determining if a frame is within a range of transfer for an Exchange; and creating (or appending if not the first out-of-order frame) an out of order list if the current frame is a first out of order frame. The method also includes, determining if an entry in an out of order list has a relative offset value of zero; determining if at least one entry has a relative offset value equal to a total transfer length of an Exchange; and determining if every non-zero starting relative offset has a matching entry. The method also scans an out of order list and combines a last entry with an entry whose starting point matches the end point of the last entry.
    Type: Grant
    Filed: October 1, 2004
    Date of Patent: March 9, 2010
    Assignee: QLOGIC, Corporation
    Inventors: Ben K. Hui, Sanjaya Anand
  • Patent number: 7668177
    Abstract: Method and system for an adapter coupled to a network via a network link is provided. The method includes using a first selectable mode and a second selectable mode to provide quality of service to a plurality of applications executed by one or more computing system. In the first selectable mode, the quality of service is based on allocating bandwidth of the network link and dynamically adjusting an initial priority assigned to a plurality of queues, each queue being associated with an application from among a plurality of applications. In the second selectable mode, the quality of service is based on a user assigning a priority to each of the plurality of applications and the adapter determines a number of input/output (I/O) requests it needs to process within a duration and then transfers information based on the determined number of I/O requests and the assigned priority.
    Type: Grant
    Filed: January 31, 2007
    Date of Patent: February 23, 2010
    Assignee: QLOGIC, Corporation
    Inventors: Darren L. Trapp, Sanjaya Anand, Jerald K. Alston
  • Patent number: 7234101
    Abstract: A method and system for performing data integrity process is provided. The method includes selecting a cyclic redundancy code (“CRC”) mode from amongst append, validate and keep, and validate and remove mode. If the append mode is selected, then CRC is appended after each data block boundary. A CRC seed value is incremented for each data block providing a unique CRC value for each data block. If validate and keep mode is selected, then CRC accompanying any data is compared to CRC that may have been accumulated. If validate and remove mode is selected, then CRC is first validated and then CRC is removed before data is sent out. The system includes CRC logic that allows firmware running on an adapter to select one of plural CRC modes including append, validate and keep, and validate and remove mode.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: June 19, 2007
    Assignee: QLOGIC, Corporation
    Inventors: Dharma R. Konda, Kathy K. Caballero, Sanjaya Anand, Ashish Bhargava, Rajendra R. Gandhi, Kuangfu David Chu, Cam Le
  • Publication number: 20060075165
    Abstract: A method and system for processing out of order frames received by a host bus adapter is provided. The method includes, determining if a current frame is out of order; determining if a frame is within a range of transfer for an Exchange; and creating (or appending if not the first out-of-order frame) an out of order list if the current frame is a first out of order frame. The method also includes, determining if an entry in an out of order list has a relative offset value of zero; determining if at least one entry has a relative offset value equal to a total transfer length of an Exchange; and determining if every non-zero starting relative offset has a matching entry. The method also scans an out of order list and combines a last entry with an entry whose starting point matches the end point of the last entry.
    Type: Application
    Filed: October 1, 2004
    Publication date: April 6, 2006
    Inventors: Ben Hui, Sanjaya Anand