Patents by Inventor Sanjay Kumar Mishra

Sanjay Kumar Mishra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor memory device that can relieve defective address
    Patent number: 7826241
    Abstract: A pre-decoded address is generated at a high speed in a semiconductor memory device. The device comprises a pre-decoder (210) for generating a first pre-decoded address (PDA1) by pre-decoding the input address (ADD), a CAM circuit (220) for activating the match signal (MT) by responding to the indication of a defective memory cell by the input address (ADD), a ROM circuit (230) for outputting a second pre-decoded address (PDA2) and an enable signal (ES) in response to the activation of the match signal (MT), and a multiplexer (240) for selecting either the first or second pre-decoded address (PDA1 or PDA2) on the basis of the enable signal (ES). According to the present invention, there is no need to use a circuit with numerous stages as there is in substituted logic; accordingly, pre-decoded addresses can be generated at a high speed.
    Type: Grant
    Filed: August 15, 2008
    Date of Patent: November 2, 2010
    Assignee: Elpida Memory, Inc.
    Inventors: Ankur Goel, Krishman S. Rengarajan, Sahadevan A. Kumaran, Sanjay Kumar Mishra
  • Semiconductor memory device that can relieve defective address
    Publication number: 20090168478
    Abstract: A pre-decoded address is generated at a high speed in a semiconductor memory device. The device comprises a pre-decoder (210) for generating a first pre-decoded address (PDA1) by pre-decoding the input address (ADD), a CAM circuit (220) for activating the match signal (MT) by responding to the indication of a defective memory cell by the input address (ADD), a ROM circuit (230) for outputting a second pre-decoded address (PDA2) and an enable signal (ES) in response to the activation of the match signal (MT), and a multiplexer (240) for selecting either the first or second pre-decoded address (PDA1 or PDA2) on the basis of the enable signal (ES) According to the present invention, there is no need to use a circuit with numerous stages as there is in substituted logic; accordingly, pre-decoded addresses can be generated at a high speed.
    Type: Application
    Filed: August 15, 2008
    Publication date: July 2, 2009
    Applicant: Elpida Memory, Inc.
    Inventors: Ankur Goel, Krishman S. Rengarajan, Sahadevan A. Kumaran, Sanjay Kumar Mishra