Abstract: Compounds of Formula (I), their preparation and use in preventing or treating bacterial infection is disclosed.

Abstract: Static random access memory (SRAM) circuits are used in most digital integrated circuits to store digital data bits. SRAM memory circuits are generally read by decoding an address, reading from an addressed memory cell using a set of bit lines, outputting data from the read memory cell, and precharging the bit lines for a subsequent memory cycle. To handle memory operations faster, a bit line multiplexing system is proposed. Two sets of bit lines are coupled to each memory cell and each set of bit lines are used for memory operations in alternating memory cycles. During a first memory cycle, a first set of bit lines accesses the memory array while precharging a second set of bit lines. Then during a second memory cycle following the first memory cycle, the first set of bit lines are precharged while the second set of bit lines accesses the memory array to read data.

Abstract: Designing memory subsystems for integrated circuits can be time-consuming and costly task. To reduce development time and costs, an automated system and method for designing and constructing high-speed memory operations is disclosed. The automated system accepts a set of desired memory characteristics and then methodically selects different potential memory system design types and different implementations of each memory system design type. The potential memory system design types may include traditional memory systems, optimized traditional memory systems, intelligent memory systems, and hierarchical memory systems. A selected set of proposed memory systems that meet the specified set of desired memory characteristics is output to a circuit designer. When a circuit designer selects a proposed memory system, the automated system generates a complete memory system design, a model for the memory system, and a test suite for the memory system.

Abstract: Multi-port memory circuits are often required within modern digital integrated circuits to store data. Multi-port memory circuits allow multiple memory users to access the same memory cell simultaneously. Multi-port memory circuits are generally custom-designed in order to obtain the best performance or synthesized with logic synthesis tools for quick design. However, these two options for creating multi-port memory give integrated circuit designers a stark choice: invest a large amount of time and money to custom design an efficient multi-port memory system or allow logic synthesis tools to inefficiently create multi-port memory. An intermediate solution is disclosed that allows an efficient multi-port memory array to be created largely using standard circuit cell components and register transfer level hardware design language code.

Abstract: Monitoring and repairing memory includes selecting a first memory bank comprising a plurality of memory cells to analyze. The plurality of memory cells are copied from the first memory bank to a second memory bank, wherein a request to access the first memory bank is redirected to the second memory bank. A determination is made whether the first memory bank comprises an error of the memory cell.

Abstract: Designing memory subsystems for integrated circuits can be time-consuming and costly task. To reduce development time and costs, an automated system and method for designing and constructing high-speed memory operations is disclosed. The automated system accepts a set of desired memory characteristics and then methodically selects different potential memory system design types and different implementations of each memory system design type. The potential memory system design types may include traditional memory systems, optimized traditional memory systems, intelligent memory systems, and hierarchical memory systems. A selected set of proposed memory systems that meet the specified set of desired memory characteristics is output to a circuit designer. When a circuit designer selects a proposed memory system, the automated system generates a complete memory system design, a model for the memory system, and a test suite for the memory system.

Abstract: A method for identifying non-orthogonal roles (112, 114, 116, 118) in an access control system (100). The method can include, for at least one policy (Pn,i) defined for a first role (112) in the access control system, automatically determining whether there is at least one policy (Pm,j) defined in a second role that conflicts with the policy defined in the first role. The method also can include, responsive to determining that the policy defined in the second role conflicts with the policy defined in the first role, providing a conflict indicator.

Abstract: A method and system for managing objects in a O&M RBAC system includes a first step of dynamically discovering an object and associated command actions by the RBAC system. A next step includes defining roles and tasks to users assigning authorization privileges for the object. A next step includes updating a graphical user interface with information about the objects, roles, tasks, and command actions. A next step includes adding information about the objects, roles, tasks, and command actions to a database for the network. A next step includes entering a command with an action from a user. A next step includes determining a role of a requesting user. A next step includes comparing the role against the database to find authorization to execute the task and action against the object.

Abstract: A method is disclosed for Simple Network Management Protocol (SNMP) bulk information processing. A request for a plurality of object instances stored in a storage space is received. The request specifies a condition and a maximum number of repetitions. The values of one or more object instances of the plurality of object instances are retrieved. The retrieval of object instance values is terminated when the condition is satisfied even though the maximum number of repetitions is not reached. For example, the condition may be specified by one or more pairs of Object Identifier (OID) values, wherein each pair is represented by a starting OID value and an ending OID value. In this example, the condition is satisfied when an OID value of an object instance that is retrieved is not lexicographically between the starting OID value and the ending OID value of any pair of the one or more pairs.