Patents by Inventor Sanjeev Maheshwari

Sanjeev Maheshwari has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9787509
    Abstract: An apparatus including a receiver coupled to receive an input signal from a communication link and operable to employ decision feedback equalization to the input signal of the communication link and generate an edge sample signal. The apparatus also includes a timing recovery module coupled to the receiver and operable to receive the edge sample signal and use the edge sample signal to generate a data sampling phase signal, wherein the edge sample signal influences a settling point of the data sampling phase signal.
    Type: Grant
    Filed: January 5, 2016
    Date of Patent: October 10, 2017
    Assignee: Nvidia Corporation
    Inventors: Lizhi Zhong, Vishnu Balan, Arif Al Amin, Sanjeev Maheshwari
  • Publication number: 20160226684
    Abstract: An apparatus including a receiver coupled to receive an input signal from a communication link and operable to employ decision feedback equalization to the input signal of the communication link and generate an edge sample signal. The apparatus also includes a timing recovery module coupled to the receiver and operable to receive the edge sample signal and use the edge sample signal to generate a data sampling phase signal, wherein the edge sample signal influences a settling point of the data sampling phase signal.
    Type: Application
    Filed: January 5, 2016
    Publication date: August 4, 2016
    Inventors: Lizhi Zhong, Vishnu Balan, Arif Al Amin, Sanjeev Maheshwari
  • Patent number: 9231802
    Abstract: An apparatus including a receiver coupled to receive an input signal from a communication link and operable to employ decision feedback equalization to the input signal of the communication link and generate an edge sample signal. The apparatus also includes a timing recovery module coupled to the receiver and operable to receive the edge sample signal and use the edge sample signal to generate a data sampling phase signal, wherein the edge sample signal influences a settling point of the data sampling phase signal.
    Type: Grant
    Filed: December 26, 2012
    Date of Patent: January 5, 2016
    Assignee: NVIDIA CORPORATION
    Inventors: Lizhi Zhong, Vishnu Balan, Arif Al Amin, Sanjeev Maheshwari
  • Patent number: 9083577
    Abstract: A sampler circuit for a decision feedback equalizer and a method of use thereof. One embodiment of the sampler circuit includes: (1) a first sampler portion including a series-coupled first master regeneration latch and first slave latch, (2) a second sampler portion including a series-coupled second master regeneration latch and second slave latch, and (3) a first feedback circuit coupled to a first node between the first master regeneration latch and the first slave latch and operable to provide a feedback signal to the second master regeneration latch to cause a bias charge to be built up therefor.
    Type: Grant
    Filed: May 17, 2013
    Date of Patent: July 14, 2015
    Assignee: Nvidia Corporation
    Inventors: Sanjeev Maheshwari, Vishnu Balan, Arif Amin
  • Publication number: 20140341268
    Abstract: A sampler circuit for a decision feedback equalizer and a method of use thereof. One embodiment of the sampler circuit includes: (1) a first sampler portion including a series-coupled first master regeneration latch and first slave latch, (2) a second sampler portion including a series-coupled second master regeneration latch and second slave latch, and (3) a first feedback circuit coupled to a first node between the first master regeneration latch and the first slave latch and operable to provide a feedback signal to the second master regeneration latch to cause a bias charge to be built up therefor.
    Type: Application
    Filed: May 17, 2013
    Publication date: November 20, 2014
    Inventors: Sanjeev Maheshwari, Vishnu Balan, Arif Amin
  • Publication number: 20140177693
    Abstract: An apparatus including a receiver coupled to receive an input signal from a communication link and operable to employ decision feedback equalization to the input signal of the communication link and generate an edge sample signal. The apparatus also includes a timing recovery module coupled to the receiver and operable to receive the edge sample signal and use the edge sample signal to generate a data sampling phase signal, wherein the edge sample signal influences a settling point of the data sampling phase signal.
    Type: Application
    Filed: December 26, 2012
    Publication date: June 26, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Lizhi Zhong, Vishnu Balan, Arif Al Amin, Sanjeev Maheshwari
  • Patent number: 8451064
    Abstract: Apparatus and methods are provided for oscillators having adjustable gain. An exemplary oscillator module comprises a first node for a first voltage, a control node for a control signal, and oscillator circuitry coupled to the first node and the control node. The oscillator circuitry generates an output signal with a first oscillation frequency based on the first voltage, and in response to the control signal being asserted, the oscillator circuitry generates the output signal with a second oscillation frequency based on the first voltage. The second oscillation frequency is greater than the first oscillation frequency.
    Type: Grant
    Filed: October 7, 2010
    Date of Patent: May 28, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Sanjeev Maheshwari, Emerson Fang, Sanjeev Aggarwal
  • Patent number: 8269533
    Abstract: Apparatus, systems and methods are provided for digital phase-locked loops. A digital phase-locked loop comprises an oscillator module configured to generate an output signal and a phase detection module coupled to the oscillator module. The phase detection module is configured to signal the oscillator module to adjust a frequency of the output signal by a first amount when a phase difference between a reference signal and the output signal is less than a threshold amount, and signal the oscillator module to adjust the frequency by a greater amount when the phase difference is greater than the threshold amount.
    Type: Grant
    Filed: September 3, 2010
    Date of Patent: September 18, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Sanjeev Maheshwari, Emerson Fang
  • Publication number: 20120086482
    Abstract: Apparatus and methods are provided for oscillators having adjustable gain. An exemplary oscillator module comprises a first node for a first voltage, a control node for a control signal, and oscillator circuitry coupled to the first node and the control node. The oscillator circuitry generates an output signal with a first oscillation frequency based on the first voltage, and in response to the control signal being asserted, the oscillator circuitry generates the output signal with a second oscillation frequency based on the first voltage. The second oscillation frequency is greater than the first oscillation frequency.
    Type: Application
    Filed: October 7, 2010
    Publication date: April 12, 2012
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Sanjeev MAHESHWARI, Emerson FANG, Sanjeev AGGARWAL
  • Publication number: 20120056653
    Abstract: Apparatus, systems and methods are provided for digital phase-locked loops. A digital phase-locked loop comprises an oscillator module configured to generate an output signal and a phase detection module coupled to the oscillator module. The phase detection module is configured to signal the oscillator module to adjust a frequency of the output signal by a first amount when a phase difference between a reference signal and the output signal is less than a threshold amount, and signal the oscillator module to adjust the frequency by a greater amount when the phase difference is greater than the threshold amount.
    Type: Application
    Filed: September 3, 2010
    Publication date: March 8, 2012
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Sanjeev MAHESHWARI, Emerson FANG
  • Patent number: 7826998
    Abstract: A method of measuring the temperature of device under test includes the steps of injecting a first current into an on-chip diode wherein a die containing the on-chip diode is under test. A second current is injected into the on-chip diode. A junction temperature is calculated based on the first current and the second current.
    Type: Grant
    Filed: November 15, 2005
    Date of Patent: November 2, 2010
    Assignee: Cypress Semiconductor Corporation
    Inventors: Babak Taheri, Gopal Patil, Sanjeev Maheshwari
  • Patent number: 7817761
    Abstract: An integrated circuit includes a variable delay circuit configured to generate at least one delayed clock signal based on a first clock signal and a first control signal. The integrated circuit includes a control circuit configured to generate a count value based on a second input signal and a second control signal. The first clock signal is a first version of the at least one delayed clock signal. At least one of the second input signal and the second control signal is a second version of the at least one delayed clock signal and the count value is indicative of a frequency characteristic of the at least one delayed clock signal. The integrated circuit is configured to monotonically vary the first control signal over a range of values and the count value is determined for individual values of the control signal.
    Type: Grant
    Filed: June 1, 2007
    Date of Patent: October 19, 2010
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Meei-Ling Chiang, Dwight K. Elvey, Sanjeev Maheshwari, Emerson S. Fang
  • Patent number: 7750711
    Abstract: A phase signal select circuit includes a supporting path coupled to a tri-state inverter circuit. The supporting path reduces effects of hysteresis on signal transfer. An apparatus includes at least one input node responsive to a respective one of at least one input signal. The apparatus includes at least one circuit coupled to a respective one of the at least one input node and coupled to an output node. Individual ones of the at least one circuit are configured to provide a version of the respective input signal to the output node in response to a first state of a respective select signal. The apparatus includes at least one second circuit coupled to a respective one of the at least one circuit. The at least one second circuit is configured to toggle nodes of the at least one circuit in response to a second state of the respective select signal.
    Type: Grant
    Filed: May 1, 2007
    Date of Patent: July 6, 2010
    Assignee: Globalfoundries Inc.
    Inventors: Sanjeev Maheshwari, Meei-Ling Chiang, Emerson S. Fang
  • Patent number: 7545190
    Abstract: A receive interface circuit includes a duty cycle adjustment circuit that adjusts the duty cycle of a reference clock signal based, at least in part, on a selected number of duty cycle adjustment units and a selected range of duty cycle adjustment. The duty cycle adjustment circuit may select as the reference clock signal one of a clock signal and at least a lower version of the clock signal in parallel with the duty cycle adjustment.
    Type: Grant
    Filed: May 1, 2007
    Date of Patent: June 9, 2009
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Meei-Ling Chiang, Sanjeev Maheshwari, Emerson S. Fang
  • Publication number: 20080297216
    Abstract: An integrated circuit includes a variable delay circuit configured to generate at least one delayed clock signal based on a first clock signal and a first control signal. The integrated circuit includes a control circuit configured to generate a count value based on a second input signal and a second control signal. The first clock signal is a first version of the at least one delayed clock signal. At least one of the second input signal and the second control signal is a second version of the at least one delayed clock signal and the count value is indicative of a frequency characteristic of the at least one delayed clock signal. The integrated circuit is configured to monotonically vary the first control signal over a range of values and the count value is determined for individual values of the control signal.
    Type: Application
    Filed: June 1, 2007
    Publication date: December 4, 2008
    Inventors: Meei-Ling Chiang, Dwight K. Elvey, Sanjeev Maheshwari, Emerson S. Fang
  • Publication number: 20080273528
    Abstract: A phase signal select circuit includes a supporting path coupled to a tri-state inverter circuit. The supporting path reduces effects of hysteresis on signal transfer. An apparatus includes at least one input node responsive to a respective one of at least one input signal. The apparatus includes at least one circuit coupled to a respective one of the at least one input node and coupled to an output node. Individual ones of the at least one circuit are configured to provide a version of the respective input signal to the output node in response to a first state of a respective select signal. The apparatus includes at least one second circuit coupled to a respective one of the at least one circuit. The at least one second circuit is configured to toggle nodes of the at least one circuit in response to a second state of the respective select signal.
    Type: Application
    Filed: May 1, 2007
    Publication date: November 6, 2008
    Inventors: Sanjeev Maheshwari, Meei-Ling Chiang, Emerson S. Fang
  • Publication number: 20080272814
    Abstract: A receive interface circuit includes a duty cycle adjustment circuit that adjusts the duty cycle of a reference clock signal based, at least in part, on a selected number of duty cycle adjustment units and a selected range of duty cycle adjustment. The duty cycle adjustment circuit may select as the reference clock signal one of a clock signal and at least a lower version of the clock signal in parallel with the duty cycle adjustment.
    Type: Application
    Filed: May 1, 2007
    Publication date: November 6, 2008
    Inventors: Meei-Ling Chiang, Sanjeev Maheshwari, Emerson S. Fang
  • Patent number: 7342836
    Abstract: A one-time programmable (OTP) latch circuit can include a single OTP device capable of storing a logic value in a nonvolatile fashion, or only two OTP devices in the event redundancy is desired. A latch section can latch a data value based on a comparison between a current drawn according to the one OTP device, and a reference current generated without and OTP device. An OTP device can include a gate oxide antifuse (GOAF) device.
    Type: Grant
    Filed: September 23, 2005
    Date of Patent: March 11, 2008
    Assignee: Cypress Semiconductor Corporation
    Inventors: Babak Taheri, Sanjeev Maheshwari
  • Patent number: 7319314
    Abstract: Circuits for regulating a voltage or current to a load(s).
    Type: Grant
    Filed: December 21, 2005
    Date of Patent: January 15, 2008
    Assignee: Cypress Semiconductor Corporation
    Inventors: Sanjeev Maheshwari, Babak Taheri
  • Publication number: 20070188256
    Abstract: An oscillator amplifier circuit is provided. The amplifier circuit can be used with a resonator to amplify and form a resonating oscillator. The amplifier circuit comprises an active circuit which includes an inverter and a current-controlled biasing circuit. One transistor of the inverter receives a voltage produced from the biasing circuit in order to place a gate terminal of that transistor at approximately a threshold voltage. The other transistor can be biased using a passive circuit element, such as a resistor. Therefore, both transistors are biased independent of each other within the optimal gain region. Large shunt capacitors are not required and the total current consumption is controlled through a variable resistor coupled to the source terminal of either the first transistor, second transistor, or possibly both transistors of the inverter to adjust the amplitude of the oscillating output.
    Type: Application
    Filed: February 10, 2006
    Publication date: August 16, 2007
    Inventor: Sanjeev Maheshwari