Patents by Inventor Sanjeev Ranganathan
Sanjeev Ranganathan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240078630Abstract: Embodiments described herein are generally directed to improvements relating to power, latency, bandwidth and/or performance issues relating to GPU processing/caching. According to one embodiment, a system includes a producer intellectual property (IP) (e.g., a media IP), a compute core (e.g., a GPU or an AI-specific core of the GPU), a streaming buffer logically interposed between the producer IP and the compute core. The producer IP is operable to consume data from memory and output results to the streaming buffer. The compute core is operable to perform AI inference processing based on data consumed from the streaming buffer and output AI inference processing results to the memory.Type: ApplicationFiled: October 19, 2023Publication date: March 7, 2024Applicant: Intel CorporationInventors: Subramaniam Maiyuran, Durgaprasad Bilagi, Joydeep Ray, Scott Janus, Sanjeev Jahagirdar, Brent Insko, Lidong Xu, Abhishek R. Appu, James Holland, Vasanth Ranganathan, Nikos Kaburlasos, Altug Koker, Xinmin Tian, Guei-Yuan Lueh, Changliang Wang
-
Patent number: 9277315Abstract: Systems and methods for suppressing pop-up noise in an audio signal are disclosed. The system includes a driver circuit shared by a pin interface and a complementary pin interface. A control unit is coupled to the pin interface and the complementary pin interface. To activate the pin interface, the control unit is configured to first activate the driver output at the complementary pin interface. Once the complementary pin interface achieves a preset voltage, the driver output is switched to the pin interface by the control unit. In addition, the driver circuit can be calibrated for a DC offset on the complementary pin interface by re-using calibration data calculated at the pin interface. Further, DC correction signals can be provided from a pre-biasing circuit based on the calibration data of the driver circuit.Type: GrantFiled: June 10, 2014Date of Patent: March 1, 2016Assignee: ST-Ericsson SAInventors: Sanjeev Ranganathan, Shyam Somayajula, Srinath Sridharan, Lionel Cimaz
-
Patent number: 9124354Abstract: A protection circuit protects a receiver from high-energy signals. In one exemplary embodiment, the protection circuit comprises a snapback transistor and a controller. The snapback transistor comprises a gate, a drain connected to an input of the receiver and a source connected to ground. The controller configured to connect the gate to a bias voltage to close the gate in a transmit mode, and to disconnect the gate from the bias voltage to open the gate in a receive mode. The snapback transistor is configured to enter into snapback responsive to a high energy signal at the drain to provide a current path from the drain to the source even when the gate is open and thus protect the receiver.Type: GrantFiled: April 6, 2012Date of Patent: September 1, 2015Assignee: ST-ERICSSON SAInventors: Ramkishore Ganti, Sanjeev Ranganathan, Srinath Sridharan
-
Patent number: 8892159Abstract: A multi-standard transceiver comprises a common balun, a controller, at least one first switch, and at least one second switch. The common balun comprises a primary coil and a secondary coil. The at least one first switch connects the primary coil of the balun to a first signal path associated with a first communication standard, or to a second signal path associated with a second communication standard responsive to a control signal provided by the controller. The at least one second switch connects the secondary coil of the balun to a first amplification path associated with the first communication standard, or to a second amplification path associated with the second communication standard responsive to a control signal provided by the controller. A common mixer is configured to provide upconverted signals to one of the signal paths depending on which communication standard has been selected.Type: GrantFiled: May 4, 2012Date of Patent: November 18, 2014Assignee: ST-Ericsson SAInventors: Ramkishore Ganti, Sanjeev Ranganathan, Srinath Sridharan
-
Publication number: 20140334632Abstract: Systems and methods for suppressing pop-up noise in an audio signal are disclosed. The system includes a driver circuit shared by a pin interface and a complementary pin interface. A control unit is coupled to the pin interface and the complementary pin interface. To activate the pin interface, the control unit is configured to first activate the driver output at the complementary pin interface. Once the complementary pin interface achieves a preset voltage, the driver output is switched to the pin interface by the control unit. In addition, the driver circuit can be calibrated for a DC offset on the complementary pin interface by re-using calibration data calculated at the pin interface. Further, DC correction signals can be provided from a pre-biasing circuit based on the calibration data of the driver circuit.Type: ApplicationFiled: June 10, 2014Publication date: November 13, 2014Inventors: SANJEEV RANGANATHAN, SHYAM SOMAYAJULA, SRINATH SRIDHARAN, LIONEL CIMAZ
-
Patent number: 8787588Abstract: Systems and methods for a low pin architecture to couple speakers with integrated circuits are disclosed herein. In an implementation, the low pin architecture facilitates in reducing the required pin interfaces to couple a low power speaker, a high power speaker, and earphone speakers with integrated circuits (ICs). For this, the high power speaker can be cross-coupled between the pin interfaces that are coupled to the low power speaker and the earphone speakers. These pin interfaces are driven by corresponding driver circuits. In said implementation, some of the driver circuits can be shared to drive multiple pin interfaces. These shared driver circuits include a combined cascode circuit having a first cascode circuit integrated with a second cascode circuit to reliably and selectively drive one or more of the pin interfaces.Type: GrantFiled: February 25, 2010Date of Patent: July 22, 2014Assignees: ST-Ericsson SA, ST-Ericsson PVT. Ltd.Inventors: Sanjeev Ranganathan, Shyam Somayajula, Srinath Sridharan, Arnold D'Souza, Ramkishore Ganti, Lionel Cimaz
-
Patent number: 8787597Abstract: Systems and methods for suppressing pop-up noise in an audio signal are disclosed. The system includes a driver circuit shared by a pin interface and a complementary pin interface. A control unit is coupled to the pin interface and the complementary pin interface. To activate the pin interface, the control unit is configured to first activate the driver output at the complementary pin interface. Once the complementary pin interface achieves a preset voltage, the driver output is switched to the pin interface by the control unit. In addition, the driver circuit can be calibrated for a DC offset on the complementary pin interface by re-using calibration data calculated at the pin interface. Further, DC correction signals can be provided from a pre-biasing circuit based on the calibration data of the driver circuit.Type: GrantFiled: February 25, 2010Date of Patent: July 22, 2014Assignees: St-Ericsson India Pvt. Ltd., St-Ericsson SAInventors: Sanjeev Ranganathan, Shyam Somayajula, Srinath Sridharan, Lionel Cimaz
-
Publication number: 20130116005Abstract: A multi-standard transceiver comprises a common balun, a controller, at least one first switch, and at least one second switch. The common balun comprises a primary coil and a secondary coil. The at least one first switch connects the primary coil of the balun to a first signal path associated with a first communication standard, or to a second signal path associated with a second communication standard responsive to a control signal provided by the controller. The at least one second switch connects the secondary coil of the balun to a first amplification path associated with the first communication standard, or to a second amplification path associated with the second communication standard responsive to a control signal provided by the controller. A common mixer is configured to provide upconverted signals to one of the signal paths depending on which communication standard has been selected.Type: ApplicationFiled: May 4, 2012Publication date: May 9, 2013Inventors: Ramkishore Ganti, Sanjeev Ranganathan, Srinath Sridharan
-
Publication number: 20120287969Abstract: A protection circuit protects a receiver from high-energy signals. In one exemplary embodiment, the protection circuit comprises a snapback transistor and a controller. The snapback transistor comprises a gate, a drain connected to an input of the receiver and a source connected to ground. The controller configured to connect the gate to a bias voltage to close the gate in a transmit mode, and to disconnect the gate from the bias voltage to open the gate in a receive mode. The snapback transistor is configured to enter into snapback responsive to a high energy signal at the drain to provide a current path from the drain to the source even when the gate is open and thus protect the receiver.Type: ApplicationFiled: April 6, 2012Publication date: November 15, 2012Inventors: Ramkishore Ganti, Sanjeev Ranganathan, Srinath Sridharan
-
Patent number: 7911257Abstract: A circuit includes an input terminal adapted to receive an input voltage, a MOSFET having its drain terminal and its source terminal connected together, a first switching arrangement configured to be controlled by a first clock signal and adapted to selectively couple the gate terminal to the input terminal, and a further switching arrangement configured to be controlled by a further clock signal in timing relationship with the first clock signal and adapted to selectively couple the source terminal and a first voltage which is capable of pulling carriers out of a channel when the first switching arrangement is not coupling the input terminal to the gate terminal.Type: GrantFiled: April 10, 2009Date of Patent: March 22, 2011Assignee: The Trustees of Columbia University in the city of New YorkInventors: Yannis Tsividis, Sanjeev Ranganathan
-
Publication number: 20100220875Abstract: Systems and methods for suppressing pop-up noise in an audio signal are disclosed. The system includes a driver circuit shared by a pin interface and a complementary pin interface. A control unit is coupled to the pin interface and the complementary pin interface. To activate the pin interface, the control unit is configured to first activate the driver output at the complementary pin interface. Once the complementary pin interface achieves a preset voltage, the driver output is switched to the pin interface by the control unit. In addition, the driver circuit can be calibrated for a DC offset on the complementary pin interface by re-using calibration data calculated at the pin interface. Further, DC correction signals can be provided from a pre-biasing circuit based on the calibration data of the driver circuit.Type: ApplicationFiled: February 25, 2010Publication date: September 2, 2010Applicants: ST-Ericsson India Pvt. Ltd., ST-Ericsson SAInventors: Sanjeev Ranganathan, Shyam Somayajula, Srinath Sridharan, Lionel Cimaz
-
Publication number: 20100220868Abstract: Systems and methods for a low pin architecture to couple speakers with integrated circuits are disclosed herein. In an implementation, the low pin architecture facilitates in reducing the required pin interfaces to couple a low power speaker, a high power speaker, and earphone speakers with integrated circuits (ICs). For this, the high power speaker can be cross-coupled between the pin interfaces that are coupled to the low power speaker and the earphone speakers. These pin interfaces are driven by corresponding driver circuits. In said implementation, some of the driver circuits can be shared to drive multiple pin interfaces. These shared driver circuits include a combined cascode circuit having a first cascode circuit integrated with a second cascode circuit to reliably and selectively drive one or more of the pin interfaces.Type: ApplicationFiled: February 25, 2010Publication date: September 2, 2010Applicants: ST-Ericsson India Pvt. Ltd, ST-Ericsson SAInventors: Sanjeev Ranganathan, Shyam Somayajula, Srinath Sridharan, Arnold D'Souza, Ramkishore Ganti, Lionel Cimaz
-
Publication number: 20090251196Abstract: A circuit includes an input terminal adapted to receive an input voltage, a MOSFET having its drain terminal and its source terminal connected together, a first switching arrangement configured to be controlled by a first clock signal and adapted to selectively couple the gate terminal to the input terminal, and a further switching arrangement configured to be controlled by a further clock signal in timing relationship with the first clock signal and adapted to selectively couple the source terminal and a first voltage which is capable of pulling carriers out of a channel when the first switching arrangement is not coupling the input terminal to the gate terminal.Type: ApplicationFiled: April 10, 2009Publication date: October 8, 2009Inventors: Yannis Tsividis, Sanjeev Ranganathan
-
Publication number: 20050275026Abstract: A circuit includes an input terminal adapted to receive an input voltage, a MOSFET having its drain terminal and its source terminal connected together, a first switching arrangement configured to be controlled by a first clock signal and adapted to selectively couple the gate terminal to the input terminal, and a further switching arrangement configured to be controlled by a further clock signal in timing relationship with the first clock signal and adapted to selectively couple the source terminal and a first voltage which is capable of pulling carriers out of a channel when the first switching arrangement is not coupling the input terminal to the gate terminal.Type: ApplicationFiled: May 31, 2005Publication date: December 15, 2005Inventors: Yannis Tsividis, Sanjeev Ranganathan
-
Publication number: 20020180528Abstract: A folding differential amplifier includes a switching preamplifier used to select between first and second differential amplifiers as a function of an input signal. The switching preamplifier includes first and second outputs that are coupled together by a first shorting switch having an open phase and a closed phase. The first and second outputs are held at a steady state value during the closed phase of the shorting switch and allowed to vary during the open phase of the shorting switch. First and second differential amplifiers each have first and second outputs and the first output of the first differential amplifier is coupled to the second output of the second differential amplifier. Similarly, the second output of the first differential amplifier is coupled to the first output of the second differential amplifier. These cross coupled outputs form first and second amplifier outputs respectively.Type: ApplicationFiled: June 4, 2001Publication date: December 5, 2002Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Ruben Herrera, Sanjeev Ranganathan
-
Patent number: 6480065Abstract: A folding differential amplifier includes a switching preamplifier used to select between first and second differential amplifiers as a function of an input signal. The switching preamplifier includes first and second outputs that are coupled together by a first shorting switch having an open phase and a closed phase. The first and second outputs are held at a steady state value during the closed phase of the shorting switch and allowed to vary during the open phase of the shorting switch. First and second differential amplifiers each have first and second outputs and the first output of the first differential amplifier is coupled to the second output of the second differential amplifier. Similarly, the second output of the first differential amplifier is coupled to the first output of the second differential amplifier. These cross coupled outputs form first and second amplifier outputs respectively.Type: GrantFiled: June 4, 2001Date of Patent: November 12, 2002Assignee: Texas Instruments IncorporatedInventors: Ruben Herrera, Sanjeev Ranganathan