Patents by Inventor Sanjeev S. Jahagirdar
Sanjeev S. Jahagirdar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10430310Abstract: Methods and apparatus relating to techniques for power management. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to generate a voltage/frequency curve for at least one of a core or a sub-core in a processor and manage an operating voltage level of the at least one of a core or a sub-core using the voltage/frequency curve. Other embodiments are also disclosed and claimed.Type: GrantFiled: April 1, 2017Date of Patent: October 1, 2019Assignee: INTEL CORPORATIONInventors: Nikos Kaburlasos, Balaji Vembu, Josh B. Mastronarde, Altug Koker, Eric C. Samson, Abhishek R. Appu, Kiran C. Veernapu, Joydeep Ray, Vasanth Ranganathan, Sanjeev S. Jahagirdar
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Patent number: 10429913Abstract: In one embodiment, a processor includes a plurality of domains each to operate at an independently controllable voltage and frequency, a plurality of linear regulators each to receive a first voltage from an off-chip source and controllable to provide a regulated voltage to at least one of the plurality of domains, and a plurality of selectors each coupled to one of the domains, where each selector is configured to provide a regulated voltage from one of the linear regulators or a bypass voltage to a corresponding domain. Other embodiments are described and claimed.Type: GrantFiled: August 7, 2018Date of Patent: October 1, 2019Assignee: Intel CorporationInventors: Sanjeev S. Jahagirdar, Satish K. Damaraju, Yun-Han Chen, Ryan D. Wells, Inder M. Sodhi, Vishram Sarurkar, Ken Drottar, Ashish V. Choubal, Rabiul Islam
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Patent number: 10409346Abstract: In one embodiment, a processor includes a plurality of domains each to operate at an independently controllable voltage and frequency, a plurality of linear regulators each to receive a first voltage from an off-chip source and controllable to provide a regulated voltage to at least one of the plurality of domains, and a plurality of selectors each coupled to one of the domains, where each selector is configured to provide a regulated voltage from one of the linear regulators or a bypass voltage to a corresponding domain. Other embodiments are described and claimed.Type: GrantFiled: August 7, 2018Date of Patent: September 10, 2019Assignee: Intel CorporationInventors: Sanjeev S. Jahagirdar, Satish K. Damaraju, Yun-Han Chen, Ryan D. Wells, Inder M. Sodhi, Vishram Sarurkar, Ken Drottar, Ashish V. Choubal, Rabiul Islam
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Publication number: 20190265765Abstract: Methods and apparatus relating to techniques for dynamic control of liquid cooling pumps to provide thermal cooling uniformity are described. In an embodiment, modification is made to operation of one or more of: one or more cooling pumps or one or more fans, based at least in part on comparison of one or more detected temperature or noise values at one or more components of a processor with one or more corresponding threshold values. The processor may include the logic that causes the modification and one or more sensors. The sensors are thermally or acoustically coupled to the one or more components of the processor to determine the detected temperature or noise values. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: February 26, 2019Publication date: August 29, 2019Applicant: Intel CorporationInventors: Sanjeev S. Jahagirdar, Eric J. Asperheim, Subramaniam Maiyuran, Abhishek R. Appu, Joydeep Ray, Altug Koker, Prasoonkumar Surti, Kiran C. Veernapu
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Publication number: 20190266981Abstract: Methods and apparatus relating to an adaptive multibit bus for energy optimization are described. In an embodiment, a 1-bit interconnect of a processor is caused to select between a plurality of operational modes. The plurality of operational modes comprises a first mode and a second mode. The first mode causes transmission of a single bit over the 1-bit interconnect at a first frequency and the second mode causes transmission of a plurality of bits over the 1-bit interconnect at a second frequency based at least in part on a determination that an operating voltage of the 1-bit interconnect is at a high voltage level and that the second frequency is lower than the first frequency. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: May 1, 2019Publication date: August 29, 2019Applicant: Intel CorporationInventors: Sanjeev S. Jahagirdar, Tapan A. Ganpule, Anupama A. Thaploo, Abhishek R. Appu, Joydeep Ray, Altug Koker
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Patent number: 10394564Abstract: According to one embodiment, a processor includes an instruction decoder to decode instruction and a execution unit to execute instructions, the execution unit being associated with a capture logic to periodically capture operating heuristics of the execution unit, a detection logic coupled to the execution unit to evaluate the captured operating heuristics to determine whether there is a need to adjust an operating point of the execution unit, and a control logic coupled to the detection logic and the execution unit to adjust the operating point of the execution unit based on the evaluation of the operating heuristics.Type: GrantFiled: June 30, 2017Date of Patent: August 27, 2019Assignee: Intel CorporationInventors: Inder M. Sodhi, Sanjeev S. Jahagirdar
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Publication number: 20190171270Abstract: According to one embodiment of the invention, a processor includes a power control unit, an interface to software during runtime that permits the software to set a plurality of power management constraint parameters for the power control unit during runtime of the processor without a reboot of the processor, and a storage element to store a respective lock bit for each of the plurality of power management constraint parameters to disable the interface from changing a respective constraint parameter when set.Type: ApplicationFiled: November 26, 2018Publication date: June 6, 2019Inventors: Ryan D. Wells, Sanjeev S. Jahagirdar, Inder M. Sodhi, Jeremy J. Shrall, Stephen H. Gunther, Daniel J. Ragland, Nicholas J. Adams
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Publication number: 20190155350Abstract: An apparatus includes a distribution network that includes circuitry configured to receive first power from a first voltage source and second power from a second voltage source, and to deliver power to each of a plurality of electronic circuitry blocks (ECBs), including to deliver first ECB power to a first ECB and second ECB power to a second ECB. The first ECB power includes a first portion of the first power and a first portion of the second power. The apparatus also includes power management logic to dynamically adjust the power to be provided to each ECB. Responsive to a change in a first activity level of the first ECB, the power management logic is to change the first ECB power by adjustment of the first portion of the first power and adjustment of the first portion of the second power. Other embodiments are described and claimed.Type: ApplicationFiled: January 18, 2019Publication date: May 23, 2019Inventors: Sandeep K. Venishetti, Sanjeev S. Jahagirdar, Srinivas Thota
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Patent number: 10289179Abstract: Methods and apparatus relating to techniques for dynamic control of liquid cooling pumps to provide thermal cooling uniformity are described. In an embodiment, modification is made to operation of one or more of: one or more cooling pumps or one or more fans, based at least in part on comparison of one or more detected temperature or noise values at one or more components of a processor with one or more corresponding threshold values. The processor may include the logic that causes the modification and one or more sensors, The sensors are thermally or acoustically coupled to the one or more components of the processor to determine the detected temperature or noise values. Other embodiments are also disclosed and claimed.Type: GrantFiled: April 21, 2017Date of Patent: May 14, 2019Assignee: Intel CorporationInventors: Sanjeev S. Jahagirdar, Eric J. Asperheim, Subramaniam Maiyuran, Abhishek R. Appu, Joydeep Ray, Altug Koker, Prasoonkumar Surti, Kiran C. Veernapu
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Patent number: 10290289Abstract: Methods and apparatus relating to an adaptive multibit bus for energy optimization are described. In an embodiment, a 1-bit interconnect of a processor is caused to select between a plurality of operational modes. The plurality of operational modes comprises a first mode and a second mode. The first mode causes transmission of a single bit over the 1-bit interconnect at a first frequency and the second mode causes transmission of a plurality of bits over the 1-bit interconnect at a second frequency based at least in part on a determination that an operating voltage of the 1-bit interconnect is at a high voltage level and that the second frequency is lower than the first frequency. Other embodiments are also disclosed and claimed.Type: GrantFiled: April 1, 2017Date of Patent: May 14, 2019Assignee: Intel CorporationInventors: Sanjeev S. Jahagirdar, Tapan A. Ganpule, Anupama A. Thaploo, Abishek R. Appu, Joydeep Ray, Altug Koker
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Publication number: 20190073336Abstract: A method is described that entails operating enabled cores of a multi-core processor such that both cores support respective software routines with a same instruction set, a first core being higher performance and consuming more power than a second core under a same set of applied supply voltage and operating frequency.Type: ApplicationFiled: August 14, 2018Publication date: March 7, 2019Inventors: VARGHESE GEORGE, SANJEEV S. JAHAGIRDAR, DEBORAH T. MARR
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Patent number: 10216240Abstract: An apparatus includes a distribution network that includes circuitry configured to receive first power from a first voltage source and second power from a second voltage source, and to deliver power to each of a plurality of electronic circuitry blocks (ECBs), including to deliver first ECB power to a first ECB and second ECB power to a second ECB. The first ECB power includes a first portion of the first power and a first portion of the second power. The apparatus also includes power management logic to dynamically adjust the power to be provided to each ECB. Responsive to a change in a first activity level of the first ECB, the power management logic is to change the first ECB power by adjustment of the first portion of the first power and adjustment of the first portion of the second power. Other embodiments are described and claimed.Type: GrantFiled: January 26, 2017Date of Patent: February 26, 2019Assignee: Intel CorporationInventors: Sandeep K. Venishetti, Sanjeev S. Jahagirdar, Srinivas Thota
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Patent number: 10146283Abstract: In one embodiment, a processor includes a plurality of domains each to operate at an independently controllable voltage and frequency, a plurality of linear regulators each to receive a first voltage from an off-chip source and controllable to provide a regulated voltage to at least one of the plurality of domains, and a plurality of selectors each coupled to one of the domains, where each selector is configured to provide a regulated voltage from one of the linear regulators or a bypass voltage to a corresponding domain. Other embodiments are described and claimed.Type: GrantFiled: November 6, 2017Date of Patent: December 4, 2018Assignee: Intel CorporationInventors: Sanjeev S. Jahagirdar, Satish K. Damaraju, Yun-Han Chen, Ryan D. Wells, Inder M. Sodhi, Vishram Sarurkar, Ken Drottar, Ashish V. Choubal, Rabiul Islam
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Publication number: 20180341306Abstract: In one embodiment, a processor includes a plurality of domains each to operate at an independently controllable voltage and frequency, a plurality of linear regulators each to receive a first voltage from an off-chip source and controllable to provide a regulated voltage to at least one of the plurality of domains, and a plurality of selectors each coupled to one of the domains, where each selector is configured to provide a regulated voltage from one of the linear regulators or a bypass voltage to a corresponding domain. Other embodiments are described and claimed.Type: ApplicationFiled: August 7, 2018Publication date: November 29, 2018Inventors: Sanjeev S. Jahagirdar, Satish K. Damaraju, Yun-Han Chen, Ryan D. Wells, Inder M. Sodhi, Vishram Sarurkar, Ken Drottar, Ashish V. Choubal, Rabiul Islam
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Publication number: 20180341305Abstract: In one embodiment, a processor includes a plurality of domains each to operate at an independently controllable voltage and frequency, a plurality of linear regulators each to receive a first voltage from an off-chip source and controllable to provide a regulated voltage to at least one of the plurality of domains, and a plurality of selectors each coupled to one of the domains, where each selector is configured to provide a regulated voltage from one of the linear regulators or a bypass voltage to a corresponding domain. Other embodiments are described and claimed.Type: ApplicationFiled: August 7, 2018Publication date: November 29, 2018Inventors: Sanjeev S. Jahagirdar, Satish K. Damaraju, Yun-Han Chen, Ryan D. Wells, Inder M. Sodhi, Vishram Sarurkar, Ken Drottar, Ashish V. Choubal, Rabiul Islam
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Patent number: 10139882Abstract: According to one embodiment of the invention, a processor includes a power control unit, an interface to software during runtime that permits the software to set a plurality of power management constraint parameters for the power control unit during runtime of the processor without a reboot of the processor, and a storage element to store a respective lock bit for each of the plurality of power management constraint parameters to disable the interface from changing a respective constraint parameter when set.Type: GrantFiled: June 6, 2016Date of Patent: November 27, 2018Inventors: Ryan D. Wells, Sanjeev S. Jahagirdar, Inder M. Sodhi, Jeremy J. Shrall, Stephen H. Gunther, Daniel J. Ragland, Nicholas J. Adams
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Publication number: 20180307971Abstract: In an example, an apparatus comprises a compute engine comprising a high precision component and a low precision component; and logic, at least partially including hardware logic, to receive instructions in the compute engine; select at least one of the high precision component or the low precision component to execute the instructions; and apply a gate to at least one of the high precision component or the low precision component to execute the instructions. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: April 24, 2017Publication date: October 25, 2018Applicant: Intel CorpoartionInventors: Kamal Sinha, Balaji Vembu, Eriko Nurvitadhi, Nicolas C. Galoppo Von Borries, Rajkishore Barik, Tsung-Han Lin, Joydeep Ray, Ping T. Tang, Michael S. Strickland, Xiaoming Chen, Anbang Yao, Tatiana Shpeisman, Abhishek R. Appu, Altug Koker, Farshad Akhbari, Narayan Srinivasa, Feng Chen, Dukhwan Kim, Nadathur Rajagopalan Satish, John C. Weast, Mike B. MacPherson, Linda L. Hurd, Vasanth Ranganathan, Sanjeev S. Jahagirdar
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Publication number: 20180307286Abstract: Methods and apparatus relating to techniques for dynamic control of liquid cooling pumps to provide thermal cooling uniformity are described. In an embodiment, modification is made to operation of one or more of: one or more cooling pumps or one or more fans, based at least in part on comparison of one or more detected temperature or noise values at one or more components of a processor with one or more corresponding threshold values. The processor may include the logic that causes the modification and one or more sensors, The sensors are thermally or acoustically coupled to the one or more components of the processor to determine the detected temperature or noise values. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: April 21, 2017Publication date: October 25, 2018Applicant: Intel CorporationInventors: Sanjeev S. Jahagirdar, Eric J. Asperheim, Subramaniam Maiyuran, Abhishek R. Appu, Joydeep Ray, Altug Koker, Prasoonkumar Surti, Kiran C. Veernapu
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Publication number: 20180300096Abstract: In accordance with some embodiments, the render rate is varied across and/or up and down the display screen. This may be done based on where the user is looking in order to reduce power consumption and/or increase performance. Specifically the screen display is separated into regions, such as quadrants. Each of these regions is rendered at a rate determined by at least one of what the user is currently looking at, what the user has looked at in the past and/or what it is predicted that the user will look at next. Areas of less focus may be rendered at a lower rate, reducing power consumption in some embodiments.Type: ApplicationFiled: April 17, 2017Publication date: October 18, 2018Inventors: Eric J. Asperheim, Subramaniam M. Maiyuran, Kiran C. Veernapu, Sanjeev S. Jahagirdar, Balaji Vembu, Devan Burke, Philip R. Laws, Kamal Sinha, Abhishek R. Appu, Elmoustapha Ould-Ahmed-Vall, Peter L. Doyle, Joydeep Ray, Travis T. Schluessler, John H. Feit, Nikos Kaburlasos, Jacek Kwiatkowski, Altug Koker
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Publication number: 20180299841Abstract: Methods and apparatus relating to autonomous vehicle neural network optimization techniques are described. In an embodiment, the difference between a first training dataset to be used for a neural network and a second training dataset to be used for the neural network is detected. The second training dataset is authenticated in response to the detection of the difference. The neural network is used to assist in an autonomous vehicle/driving. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: April 17, 2017Publication date: October 18, 2018Applicant: Intel CorporationInventors: Abhishek R. Appu, Altug Koker, Linda L. Hurd, Dukhwan Kim, Mike B. MacPherson, John C. Weast, Justin E. Gottschlich, Jingyi Jin, Barath Lakshmanan, Chandrasekaran Sakthivel, Michael S. Strickland, Joydeep Ray, Kamal Sinha, Prasoonkumar Surti, Balaji Vembu, Ping T. Tang, Anbang Yao, Tatiana Shpeisman, Xiaoming Chen, Vasanth Ranganathan, Sanjeev S. Jahagirdar