Abstract: An automatic artwork review system validates an artwork or a product label based on a received label specification document. Text extracted from the product label is chunked into sentences and words. Character-wise comparison is executed to identify the best match text from the label specification document for the sentence chunks from the product label. If the corresponding best match texts bears a similarity higher than a predetermined threshold to selected text including one or more sentence chunks, no errors are raised. If the similarity of the best match text to the selected text is not higher than the predetermined threshold, the specific errors occurring in the selected text and the particular portions where such errors are present are identified. The information regarding the errors can be output via one or more of an output user interface or a label compliance report.

Abstract: An automatic artwork review system validates an artwork or a product label based on a received label specification document. Text extracted from the product label is chunked into sentences and words. Character-wise comparison is executed to identify the best match text from the label specification document for the sentence chunks from the product label. If the corresponding best match texts bears a similarity higher than a predetermined threshold to selected text including one or more sentence chunks, no errors are raised. If the similarity of the best match text to the selected text is not higher than the predetermined threshold, the specific errors occurring in the selected text and the particular portions where such errors are present are identified. The information regarding the errors can be output via one or more of an output user interface or a label compliance report.

Abstract: A circuit editor generates a graphic rendering of an electronic circuit design for partial display in a visual canvas on a display unit. The circuit editor detects aberrant arrangements of circuit elements which violate predetermined circuit layout criteria, such as minimum spacing between the edges or corners of circuit elements, and forms a correction scheme to rearrange the circuit elements such that consistency with the circuit layout criteria is restored. When the aberrant arrangements are not themselves displayed in the visual canvas, the circuit editor generates visual indications of the layout violation and of the correction scheme, the latter being used to guide user correction of the violation.

Abstract: An approach is described for implementing a GUI that provides a user interface for reviewing and correcting design rule violations within a CAD program. According to some embodiments, a user may enter a serial review process which may utilize contextual information to determine where to start that review process. Further, the serial review process may enable the user to review rule violations in an individual manner for a respective object. Furthermore, a dynamic directional violation identifier may be used to identify additional errors in the direction of movement, such as by processing a set of rules and parameters with respect to objects in the direction of movement. The serial review process and the dynamic directional violation identification may be combined in a single process such that as violations are reviewed, and corrections are attempted, they may be verified to determine if they generate additional violations.

Abstract: A method, system, and computer program product for triple patterning technology (TPT) violation detection and visualization within an integrated circuit design layout are disclosed. In a first aspect, the method comprises mapping a plurality of violations of the integrated circuit design layout to a graph, generating a color graph corresponding to the graph, detecting at least one TPT violation from the color graph; and visualizing the at least one TPT violation on a layout canvas. In a second aspect, the system comprises a graph generator module for mapping a plurality of violations of the integrated circuit design layout to a graph and to generate a color graph corresponding to the graph, a detector module for detecting at least one TPT violation from the color graph, and a visualizer module for visualizing the at least one TPT violation on a layout canvas.

Abstract: Disclosed encompasses method, system, computer program product for implementing interactive checking of constraints. Various embodiments bridge schematic design environment and layout environment with a binder mapping process and utilize connectivity information from the schematic design to identify constraint violations early in the physical design stage. The method identifies or creates a layout and identifies or generates an object for a modification process. The method may take snapshot(s) of the design database or may use one or more logs for restoring the design database. The method then identifies or creates scratch pad(s) and performs modification process on the object to generate a change. The method uses scratch pad(s) and trigger(s) to perform constraint checking during the modification process to provide interactive feedback in response to the modification process before committing the change to the persistent database.

Abstract: Computer-implemented method, system and computer program product for double patterning technology (DPT) odd loops visualization within an integrated circuit design layout are disclosed. The method, system and computer program product comprise mapping all violations of the integrated circuit design layout to a graph. The method, system and computer programming product also includes partitioning the graph into a plurality of sub-graphs. Each of the plurality of sub-graphs includes multiple edges and multiple nodes. The method, system and computer product further include detecting all possible odd loops in each of the plurality of sub-graphs; and visualizing all of the odd loops in at least one of the plurality of sub-graphs.

Abstract: Disclosed are methods and systems for implementing constraint and connectivity aware physical designs. The method or system provides a connectivity-aware environment to implement electronic designs. For example, the method interactively determines whether an electronic design complies with various constraints by using connectivity information in a nearly real-time manner while the electronic design is being created in some embodiments. The method or system uses the connectivity information provided by a connectivity engine or specified by designers to present feedback to a user as to whether a newly created object or a newly modified object complies or violates certain relevant constraints in an interactive manner or in nearly real-time without having to perform such constraints checking in batch mode. The method further enables one to implement electronic designs by using connectivity information without performing extraction on layouts or rebuilding nets.

Abstract: A circuit design process is presented that includes a block placement operation, followed by global routing based upon the initial placement of the blocks. Congestion data is generated from the global routing and, in an automated process, the blocks are placed again based upon the congestion data to reduce the routing congestion of the design. This can be used as part of a custom layout design process, for example.

Abstract: A system which enables an administrator to conveniently specify statements of a web page description which may require additional processing. The administrator may select from a list of statement types, and a language grammar corresponding to the selected statement type is displayed. The administrator may provide variable data associated with the fields of the displayed language grammar, and a rule instance is created from the language grammar and the variable data. An intermediate server may determine whether each statement of a web page description matches any of the rule instances. If a match is detected, the corresponding statement is determined to potentially require additional processing (such as modification of a URL in a reverse proxy server).

Abstract: A circuit design process for the reduction of routing congestion is described. This process includes a block placement operation, an initial pin optimization for the block placement, and global routing based upon the initial pin optimization. Congestion data is generated from the global routing and, in an automated process, the pins are re-optimized, based upon the congestion data. This process can be used as part of a custom layout design process, for example.

Abstract: A system which enables an administrator to conveniently specify statements of a web page description which may require additional processing. The administrator may select from a list of statement types, and a language grammar corresponding to the selected statement type is displayed. The administrator may provide variable data associated with the fields of the displayed language grammar, and a rule instance is created from the language grammar and the variable data. An intermediate server may determine whether each statement of a web page description matches any of the rule instances. If a match is detected, the corresponding statement is determined to potentially require additional processing (such as modification of a URL in a reverse proxy server).