Patents by Inventor Sanjib Sarkar
Sanjib Sarkar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10637636Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for jitter sensing and adaptive control of parameters of clock and data recovery (CDR) circuits. A receiver component includes an adaptive CDR loop dynamic control circuit. The adaptive CDR loop dynamic control circuit is to detect first sinusoidal jitter at a first frequency and a first amplitude and update parameters of the CDR circuit to a first plurality of values based on the first frequency and the first amplitude. The adaptive CDR loop dynamic control circuit is further to detect second sinusoidal jitter at a second frequency and a second amplitude and update the parameters of the CDR circuit to a second plurality of values based on the second frequency and the second amplitude. The first sinusoidal jitter is in a first incoming data signal and the second sinusoidal jitter is in a second incoming data signal.Type: GrantFiled: March 18, 2019Date of Patent: April 28, 2020Assignee: Intel CorporationInventors: Yun He, Adhiveeraraghavan Srikanth, Sanjib Sarkar
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Publication number: 20190349184Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for jitter sensing and adaptive control of parameters of clock and data recovery (CDR) circuits. A receiver component includes an adaptive CDR loop dynamic control circuit. The adaptive CDR loop dynamic control circuit is to detect first sinusoidal jitter at a first frequency and a first amplitude and update parameters of the CDR circuit to a first plurality of values based on the first frequency and the first amplitude. The adaptive CDR loop dynamic control circuit is further to detect second sinusoidal jitter at a second frequency and a second amplitude and update the parameters of the CDR circuit to a second plurality of values based on the second frequency and the second amplitude. The first sinusoidal jitter is in a first incoming data signal and the second sinusoidal jitter is in a second incoming data signal.Type: ApplicationFiled: March 18, 2019Publication date: November 14, 2019Inventors: Yun HE, Adhiveeraraghavan SRIKANTH, Sanjib SARKAR
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Patent number: 10474607Abstract: A source device includes an adaptive link training circuity. The link training circuitry includes source capability information for link training of a link between the source device and a sink device. The source device includes a transmitter coupled to the adaptive link training circuitry to transmit the source capability information to the sink device. The adaptive link training circuitry is to initiate link training between the source device and the sink device, determine whether the link training between the source device and the sink device is unsuccessful, and in response to determining that the link training is unsuccessful, automatically adapt a setting of the link training based on the source capability information.Type: GrantFiled: May 1, 2018Date of Patent: November 12, 2019Assignee: Intel CorporationInventors: Sriram Venkatesan, Sanjib Sarkar
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Patent number: 10237051Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for jitter sensing and adaptive control of parameters of clock and data recovery (CDR) circuits. A receiver component includes an adaptive CDR loop dynamic control circuit. The adaptive CDR loop dynamic control circuit is to detect first sinusoidal jitter at a first frequency and a first amplitude and update parameters of the CDR circuit to a first plurality of values based on the first frequency and the first amplitude. The adaptive CDR loop dynamic control circuit is further to detect second sinusoidal jitter at a second frequency and a second amplitude and update the parameters of the CDR circuit to a second plurality of values based on the second frequency and the second amplitude. The first sinusoidal jitter is in a first incoming data signal and the second sinusoidal jitter is in a second incoming data signal.Type: GrantFiled: May 14, 2018Date of Patent: March 19, 2019Assignee: Intel CorporationInventors: Yun He, Adhiveeraraghavan Srikanth, Sanjib Sarkar
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Publication number: 20190044693Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for jitter sensing and adaptive control of parameters of clock and data recovery (CDR) circuits. A receiver component includes an adaptive CDR loop dynamic control circuit. The adaptive CDR loop dynamic control circuit is to detect first sinusoidal jitter at a first frequency and a first amplitude and update parameters of the CDR circuit to a first plurality of values based on the first frequency and the first amplitude. The adaptive CDR loop dynamic control circuit is further to detect second sinusoidal jitter at a second frequency and a second amplitude and update the parameters of the CDR circuit to a second plurality of values based on the second frequency and the second amplitude. The first sinusoidal jitter is in a first incoming data signal and the second sinusoidal jitter is in a second incoming data signal.Type: ApplicationFiled: May 14, 2018Publication date: February 7, 2019Inventors: Yun HE, Adhiveeraraghavan SRIKANTH, Sanjib SARKAR
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Publication number: 20190042507Abstract: A source device includes an adaptive link training circuity. The link training circuitry includes source capability information for link training of a link between the source device and a sink device. The source device includes a transmitter coupled to the adaptive link training circuitry to transmit the source capability information to the sink device. The adaptive link training circuitry is to initiate link training between the source device and the sink device, determine whether the link training between the source device and the sink device is unsuccessful, and in response to determining that the link training is unsuccessful, automatically adapt a setting of the link training based on the source capability information.Type: ApplicationFiled: May 1, 2018Publication date: February 7, 2019Inventors: Sriram Venkatesan, Sanjib Sarkar
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Patent number: 10009194Abstract: A serial input/output method and receiver include an receiver portion to receive an analog differential serial input and sample the input to provide data and error signals, an equalization feedback loop responsive to the data and error signals to adjust the receiver portion, a phase feedback mechanism separate from the equalization feedback loop to provide a phase error, and a clock data recovery block coupled to receive the phase error to perform timing recovery for the receiver portion independent of the equalization feedback to adjust the sampling.Type: GrantFiled: October 24, 2016Date of Patent: June 26, 2018Assignee: Intel CorporationInventors: Yun He, Sanjib Sarkar, Fei Deng, Senthil Arun Singaravelu, Narender Nagulapally, Pranali Shah
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Patent number: 9697792Abstract: Systems and methods of the present disclosure include transmitter devices. The transmitter devices include a high-speed driver domain having a low-dropout regulator. The low-dropout regulator reduces a voltage level from an input voltage source to the high-speed driver domain. In addition, the transmitter devices include a low-speed driver domain. The low-speed driver domain includes a pre-driver which reduces a voltage level from an input voltage source to the low-speed driver domain.Type: GrantFiled: September 18, 2014Date of Patent: July 4, 2017Assignee: INTEL CORPORATIONInventors: Sriram Venkatesan, Sanjib Sarkar
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Publication number: 20170070370Abstract: A serial input/output method and receiver include an receiver portion to receive an analog differential serial input and sample the input to provide data and error signals, an equalization feedback loop responsive to the data and error signals to adjust the receiver portion, a phase feedback mechanism separate from the equalization feedback loop to provide a phase error, and a clock data recovery block coupled to receive the phase error to perform timing recovery for the receiver portion independent of the equalization feedback to adjust the sampling.Type: ApplicationFiled: October 24, 2016Publication date: March 9, 2017Inventors: Yun He, Sanjib Sarkar, Fei Deng, Senthil Arun Singaravelu, Narender Nagulapally, Pranali Shah
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Patent number: 9521021Abstract: Techniques for adaptive backchannel equalization. A total equalization value is determined over a preselected training period. A total balance equalization value is determined over the preselected training period. A transmitter equalization coefficient is determined based on the total equalization value and the total balance equalization value. Data is transmitted over a serial link using the transmitter equalization coefficient.Type: GrantFiled: September 20, 2015Date of Patent: December 13, 2016Assignee: Intel CorporationInventors: Yun He, Sanjib Sarkar
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Patent number: 9479364Abstract: A serial input/output method and receiver include an receiver portion to receive an analog differential serial input and sample the input to provide data and error signals, an equalization feedback loop responsive to the data and error signals to adjust the receiver portion, a phase feedback mechanism separate from the equalization feedback loop to provide a phase error, and a clock data recovery block coupled to receive the phase error to perform timing recovery for the receiver portion independent of the equalization feedback to adjust the sampling.Type: GrantFiled: May 13, 2015Date of Patent: October 25, 2016Assignee: Intel CorporationInventors: Yun He, Sanjib Sarkar, Fei Deng, Senthil Arun Singaravelu, Narender Nagulapally, Pranali Shah
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Patent number: 9436244Abstract: Methods and apparatus related to adaptive control loop protection for fast and robust recovery from low-power states in high speed serial I/O applications are described. In some embodiments, a first bit pattern is detected, at a first agent, that indicates a speculative entry by a second agent into a low power consumption state and one or more control loops are frozen. A second bit pattern is detected (after entering the low power consumption state) that indicates exit from the low power consumption state by the second agent and the one or more control loops are unfrozen (e.g., in a specific order). Other embodiments are also claimed and/or disclosed.Type: GrantFiled: March 15, 2013Date of Patent: September 6, 2016Assignee: Intel CorporationInventors: Yun He, Narender R. Nagulapally, Sanjib Sarkar, Ivan Herrera Mejia, Ruchira K. Liyanage
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Publication number: 20160086564Abstract: Systems and methods of the present disclosure include transmitter devices. The transmitter devices include a high-speed driver domain having a low-dropout regulator. The low-dropout regulator reduces a voltage level from an input voltage source to the high-speed driver domain. In addition, the transmitter devices include a low-speed driver domain. The low-speed driver domain includes a pre-driver which reduces a voltage level from an input voltage source to the low-speed driver domain.Type: ApplicationFiled: September 18, 2014Publication date: March 24, 2016Inventors: Sriram Venkatesan, Sanjib Sarkar
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Publication number: 20160080179Abstract: Techniques for adaptive backchannel equalization. A total equalization value is determined over a preselected training period. A total balance equalization value is determined over the preselected training period. A transmitter equalization coefficient is determined based on the total equalization value and the total balance equalization value. Data is transmitted over a serial link using the transmitter equalization coefficient.Type: ApplicationFiled: September 20, 2015Publication date: March 17, 2016Inventors: Yun He, Sanjib Sarkar
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Patent number: 9143369Abstract: Techniques for adaptive backchannel equalization. A total equalization value is determined over a preselected training period. A total balance equalization value is determined over the preselected training period. A transmitter equalization coefficient is determined based on the total equalization value and the total balance equalization value. Data is transmitted over a serial link using the transmitter equalization coefficient.Type: GrantFiled: May 20, 2013Date of Patent: September 22, 2015Assignee: Intel CorporationInventors: Yun He, Sanjib Sarkar
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Publication number: 20150249556Abstract: A serial input/output method and receiver include an receiver portion to receive an analog differential serial input and sample the input to provide data and error signals, an equalization feedback loop responsive to the data and error signals to adjust the receiver portion, a phase feedback mechanism separate from the equalization feedback loop to provide a phase error, and a clock data recovery block coupled to receive the phase error to perform timing recovery for the receiver portion independent of the equalization feedback to adjust the sampling.Type: ApplicationFiled: May 13, 2015Publication date: September 3, 2015Inventors: Yun He, Sanjib Sarkar, Fei Deng, Senthil Arun Singaravelu, Narender Nagulapally, Pranali Shah
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Patent number: 9048999Abstract: A serial input/output method and receiver include an receiver portion to receive an analog differential serial input and sample the input to provide data and error signals, an equalization feedback loop responsive to the data and error signals to adjust the receiver portion, a phase feedback mechanism separate from the equalization feedback loop to provide a phase error, and a clock data recovery block coupled to receive the phase error to perform timing recovery for the receiver portion independent of the equalization feedback to adjust the sampling.Type: GrantFiled: April 19, 2012Date of Patent: June 2, 2015Assignee: Intel CorporationInventors: Yun He, Sanjib Sarkar, Fei Deng, Senthil Arun Singaravelu, Narender Nagulapally, Pranali Shah
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Publication number: 20140307769Abstract: A serial input/output method and receiver include an receiver portion to receive an analog differential serial input and sample the input to provide data and error signals, an equalization feedback loop responsive to the data and error signals to adjust the receiver portion, a phase feedback mechanism separate from the equalization feedback loop to provide a phase error, and a clock data recovery block coupled to receive the phase error to perform timing recovery for the receiver portion independent of the equalization feedback to adjust the sampling.Type: ApplicationFiled: April 19, 2012Publication date: October 16, 2014Inventors: Yun He, Sanjib Sarkar, Fei Deng, Senthil Arun Singaravelu, Narender Nagulapally, Pranali Shah
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Publication number: 20140281668Abstract: Methods and apparatus related to adaptive control loop protection for fast and robust recovery from low-power states in high speed serial I/O applications are described. In some embodiments, a first bit pattern is detected, at a first agent, that indicates a speculative entry by a second agent into a low power consumption state and one or more control loops are frozen. A second bit pattern is detected (after entering the low power consumption state) that indicates exit from the low power consumption state by the second agent and the one or more control loops are unfrozen (e.g., in a specific order). Other embodiments are also claimed and/or disclosed.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Inventors: Yun He, Narender R. Nagulapally, Sanjib Sarkar, Ivan Herrera Mejia, Ruchira K. Liyanage
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Publication number: 20140269881Abstract: Techniques for adaptive backchannel equalization. A total equalization value is determined over a preselected training period. A total balance equalization value is determined over the preselected training period. A transmitter equalization coefficient is determined based on the total equalization value and the total balance equalization value. Data is transmitted over a serial link using the transmitter equalization coefficient.Type: ApplicationFiled: May 20, 2013Publication date: September 18, 2014Inventors: YUN HE, SANJIB SARKAR