Abstract: An interlevel dielectric layer (ILD) comprises a low-k dielectric layer; and a low-k dielectric film, deposited under compressive stress, atop the dielectric layer. The dielectric layer comprises a low-k material, such as an organosilicon glass (OSG) or a SiCOH material. The dielectric film has a thickness, which is 2%-10% of the thickness of the dielectric layer, has a similar chemical composition to the dielectric layer, but has a different morphology than the dielectric layer. The dielectric film is deposited under compressive stress, in situ, at or near the end of the dielectric layer deposition by altering a process that was used to deposit the low-k dielectric layer.

Abstract: A method for forming a copper interconnect on an integrated circuit (IC) begins by forming a dielectric layer (20) having an opening. A tantalum-based barrier layer (21), such as TaN or TaSiN, is formed within the opening in the layer (20). A copper layer (22) is formed over the barrier layer (21). A first CMP process is used to polish the copper (22) to expose portions of the barrier (21). A second CMP process which is different from the first CMP process is then used to polish exposed portions of the layer (21) faster than the dielectric layer (20) or the copper layer (22). After this two-step CMP process, a copper interconnect having a tantalum-based barrier is formed across the integrated circuit substrate (12).

Abstract: A method for chemical mechanical polishing (CMP) a copper layer (22) begins by forming the copper layer (22). The copper layer (22) is then exposed to a slurry (24). The slurry (24) contains an oxidizing agent such as H.sub.2 O.sub.2, a carboxylate salt such as ammonium citrate, an abrasive slurry such as alumna abrasive, an optional triazole or triazole derivative, and a remaining balance of a solvent such as deionized water. The use of the slurry (24) polishes the copper layer (22) with a high rate of removal whereby pitting and corrosion of the copper layer (22) is reduced and good copper interconnect planarity is achieved. This slurry (24) has good selectivity of copper to oxide, and results in copper devices which have good electrical performance. In addition, disposal of the slurry (24) is not environmentally difficult since the slurry (24) is environmentally sound when compared to other prior art slurries.

Abstract: A polishing system (10) is used to polish a semiconductor wafer (16) in accordance with the present invention. Polishing system (10) includes a wafer carrier (14) which includes a modulation unit (20). Modulation unit (20) includes a plurality of capacitors made up of a flexible lower plate (22) and a plurality of smaller upper plate segments (24). A controller (40) monitors the capacitance between each smaller upper plate segment (24) and lower plate (22), and compares the measured capacitance against a predefined set capacitance. To the extent the measured capacitance and predefined capacitance are different, controller (40) adjusts the voltage being applied to the respective upper plate segment (24) so that the measured capacitance and predefined capacitance are aligned. Thus, the present invention is able to achieve dynamic and localized control of the shape of the wafer as it is being polished.