Abstract: An interconnect structure for a semiconductor device includes an organic, low dielectric constant (low-k) dielectric layer formed over a lower metallization level. A via formed is within the low-k dielectric layer, the via connecting a lower metallization line formed in the lower metallization level with an upper metallization line formed in an upper metallization level. The via is surrounded by a structural collar selected from a material having a coefficient of thermal expansion (CTE) so as to protect the via from shearing forces following a thermal expansion of the low-k dielectric layer.

Abstract: A detection system and method including a means for performing a test on a semiconductor device and obtaining test data therefrom. The semiconductor device includes an insulating layer, a hard mask layer on a surface of the insulating layer, and a plurality of electrically conductive lines within a trench in the insulating layer. The insulating layer comprises a first dielectric material. The hard mask layer comprises a second dielectric material. The dielectric constant of the second dielectric material exceeds the dielectric constant of the first dielectric material or the second dielectric material comprises an element that is not comprised by the first dielectric material. The test data is a function of a spatial distribution of the hard mask layer on the surface of the insulating layer. The detection system and method includes a means for determining from the test data a measure of the spatial distribution of the hard mask layer on the surface of the insulating layer.

Abstract: An interconnect structure for a semiconductor device includes an organic, low dielectric constant (low-k) dielectric layer formed over a lower metallization level. A via formed is within the low-k dielectric layer, the via connecting a lower metallization line formed in the lower metallization level with an upper metallization line formed in an upper metallization level. The via is surrounded by a structural collar selected from a material having a coefficient of thermal expansion (CTE) so as to protect the via from shearing forces following a thermal expansion of the low-k dielectric layer.

Abstract: A method of chemical mechanical planarization of a semiconductor device provides a semiconductor device having a device front surface and a device back surface with the device front surface being a top surface of a second metal layer. A first planarizing step planarizes the device front surface with a first medium to expose a device second front surface, where the first medium comprises a first abrasive component and a first chemical solution. A rinsing step then rinses the device back surface with water. A second planarizing step then planarizes the device second front surface with a second medium where the second medium comprises a second abrasive component and a second chemical solution.

Abstract: Physical properties of alumina particles in a chemical-mechanical polishing slurry delivery loop (28) are measured using a titration technique (44). Examples of the physical properties include crystallographic phase, surface charge, and surface charge density. The physical properties are correlated to a polishing rate (46). Specification limits are generated using the correlated data (482 and 486). The specification limits are used to determine if no adjustments are required to the polishing parameters (484), if adjustments are required to polishing parameters (488) or if the slurry requires replacement (489). This process can be automated and integrated into a conventional chemical-mechanical polishing processing system (20).