Patents by Inventor Sanjiv Sambandan
Sanjiv Sambandan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8040729Abstract: A memory cell array including a data line; a capacitor; and a transistor coupled between the data line and the capacitor. At least one of the capacitor and the transistor includes a material with a mutable electrical characteristic. A memory cell array including a first transistor coupled between a first node, a second node, and a third node; and a second transistor coupled between the second node and a fourth node. The first transistor includes a material with a mutable electrical characteristic.Type: GrantFiled: November 19, 2009Date of Patent: October 18, 2011Assignee: Palo Alto Research Center IncorporatedInventors: William S. Wong, Sanjiv Sambandan, Tse Nga Ng, Robert A. Street
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Patent number: 8040722Abstract: A memory cell array including a data line; a capacitor; and a transistor coupled between the data line and the capacitor. At least one of the capacitor and the transistor includes a material with a mutable electrical characteristic. A memory cell array including a first transistor coupled between a first node, a second node, and a third node; and a second transistor coupled between the second node and a fourth node. The first transistor includes a material with a mutable electrical characteristic.Type: GrantFiled: November 19, 2009Date of Patent: October 18, 2011Assignee: Palo Alto Research Center IncorporatedInventors: William S. Wong, Sanjiv Sambandan, Tse Nga Ng, Robert A. Street
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Patent number: 8000613Abstract: A system, including an improved sensor, for determining toner particle uniformity is described. The sensor measures toner particle charge, typically be having the charge on the toner particle control a current flow through the channel of a thin film transistor. By measuring the charge on many toner particles, the system determines whether sufficient toner degradation has occurred that the toner should be replaced. The sensor is particularly suitable for being formed on a thin diagnostic sheet that is input through the paper path of a printing system.Type: GrantFiled: December 18, 2008Date of Patent: August 16, 2011Assignee: Palo Alto Research Center IncorporatedInventors: William S Wong, Michael L Chabinyc, Sanjiv Sambandan, Pengfei Qi
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Publication number: 20110147742Abstract: A thin film field effect transistor is disclosed which provides improved time-based channel stability. The field effect transistor includes first and second disordered semiconductor layers separated by an insulator. In an embodiment a carrier injection terminal is provided in a thin semiconductor layer closest to the gate terminal. An electric field is established in the thin semiconductor layer. At sufficient field strength, the electric field extends into the second semiconductor layer, which is in contact with the source and drain terminals. At sufficient field strength a channel is established in the second semiconductor layer, permitting current to flow between source and drain terminals. Above a certain gate voltage, there is sufficient free charge is induced in the first semiconductor layer so that the field does not extend into the second semiconductor, effectively shutting off current between source and drain. Single-device transition detection (as well as other applications) may be obtained.Type: ApplicationFiled: December 18, 2009Publication date: June 23, 2011Applicant: Palo Alto Research Center IncorporatedInventors: Sanjiv Sambandan, Ana Claudia Arias, Gregory Lewis Whiting
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Publication number: 20110095272Abstract: An organic non-volatile memory array including multiple pixels and associated signal lines that are disposed on and between a substrate, a single ferroelectric dielectric layer, and a single organic dielectric layer, where each pixel includes a ferroelectric field-effect transistor (FeFET) and at least one organic thin-film field effect transistor (FET) that are connected to associated signal lines in a way that facilitates addressable reading and writing to the FeFET of a selected pixel without disturbing the data stored in adjacent pixels. Analog data storage in the FeFET array is also introduced that does not require analog-to-digital conversion of the stored data.Type: ApplicationFiled: October 28, 2009Publication date: April 28, 2011Applicant: Palo Alto Research Center IncorporatedInventors: Tse Nga Ng, Ana C. Arias, Sanjiv Sambandan, Robert A. Street, Jurgen H. Daniel
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Publication number: 20110027946Abstract: A modified coffee-stain method for producing self-organized line structures and other very fine features that involves disposing a solution puddle on a target substrate, and then controlling the peripheral boundary shape of the puddle using a control structure that contacts the puddle's upper surface. The solution is made up of a fine particle solute dispersed in a liquid solvent wets and becomes pinned to both the target substrate and the control structure. The solvent is then caused to evaporate at a predetermined rate such that a portion of the solute forms a self-organized “coffee-stain” line structure on the target substrate surface that is contacted by the peripheral puddle boundary. The target structure is optionally periodically raised to generate parallel lines that are subsequently processed to form, e.g., TFTs for large-area electronic devices.Type: ApplicationFiled: October 7, 2010Publication date: February 3, 2011Applicant: Palo Alto Research Center IncorporatedInventors: Sanjiv Sambandan, Robert A. Street, Ana Claudia Arias
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Patent number: 7867916Abstract: A modified coffee-stain method for producing self-organized line structures and other very fine features that involves disposing a solution puddle on a target substrate, and then controlling the peripheral boundary shape of the puddle using a control structure that contacts the puddle's upper surface. The solution is made up of a fine particle solute dispersed in a liquid solvent wets and becomes pinned to both the target substrate and the control structure. The solvent is then caused to evaporate at a predetermined rate such that a portion of the solute forms a self-organized “coffee-stain” line structure on the target substrate surface that is contacted by the peripheral puddle boundary. The target structure is optionally periodically raised to generate parallel lines that are subsequently processed to form, e.g., TFTs for large-area electronic devices.Type: GrantFiled: June 15, 2009Date of Patent: January 11, 2011Assignee: Palo Alto Research Center IncorporatedInventors: Sanjiv Sambandan, Robert A. Street, Ana Claudia Arias
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Publication number: 20100317159Abstract: A “vertical” coffee-stain method for producing self-organized line structures and other very fine features that involves disposing a target structure in a solution made up of a fine particle solute dispersed in a liquid solvent such that a “waterline” is formed by the upper (liquid/air) surface of the solution on a targeted linear surface region of the substrate. The solvent is then caused to evaporate at a predetermined rate such that a portion of the solute forms a self-organized “coffee-stain” line structure on the straight-line portion of the substrate surface contacted by the receding waterline. The substrate and staining solution are selected such that the liquid solvent has a stronger attraction to the substrate surface than to itself to produce the required pinning and upward curving waterline. The target structure is optionally periodically raised to generate parallel lines that are subsequently processed to form, e.g., TFTs for large-area electronic devices.Type: ApplicationFiled: June 15, 2009Publication date: December 16, 2010Applicant: Palo Alto Research Center IncorporatedInventors: Sanjiv Sambandan, Robert A. Street, Ana Claudia Arias
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Publication number: 20100317160Abstract: A modified coffee-stain method for producing self-organized line structures and other very fine features that involves disposing a solution puddle on a target substrate, and then controlling the peripheral boundary shape of the puddle using a control structure that contacts the puddle's upper surface. The solution is made up of a fine particle solute dispersed in a liquid solvent wets and becomes pinned to both the target substrate and the control structure. The solvent is then caused to evaporate at a predetermined rate such that a portion of the solute forms a self-organized “coffee-stain” line structure on the target substrate surface that is contacted by the peripheral puddle boundary. The target structure is optionally periodically raised to generate parallel lines that are subsequently processed to form, e.g., TFTs for large-area electronic devices.Type: ApplicationFiled: June 15, 2009Publication date: December 16, 2010Applicant: Palo Alto Research Center IncorporatedInventors: Sanjiv Sambandan, Robert A. Street, Ana Claudia Arias
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Patent number: 7824949Abstract: A method of forming a sensor array. The method includes depositing a source/drain contact layer; depositing a semiconductor layer on the source/drain contact layer; and patterning the source/drain contact layer and the semiconductor layer substantially simultaneously, wherein the patterned semiconductor layer forms part of a sensor of the sensor array.Type: GrantFiled: December 21, 2007Date of Patent: November 2, 2010Assignee: Palo Alto Research Center IncorporatedInventors: Sanjiv Sambandan, William S. Wong, Rene A. Lujan, Scott J. Limb
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Publication number: 20100180701Abstract: A sensing device has at least two remote units mounted on an attachable tape, the remote units being mounted on separate branches of the attachable tape, a controller mounted on the attachable tape, electrical connections at least between each remote unit and the controller, the electrical connections on the attachable tape, and a surface to which the tape is attached such that the branches are separated from each other. A method of manufacturing a sensing device, including providing an attachable substrate, and fabricating electronic devices on the substrate, the electronic devices including at least two remote units, a controller and electrical connections between the remote units and the controller, and arranging the electronic devices such that at least two remote units are separated from each other.Type: ApplicationFiled: January 19, 2009Publication date: July 22, 2010Applicant: PALO ALTO RESEARCH CENTER INCORPORATEDInventors: Jurgen H. Daniel, Sanjiv Sambandan
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Publication number: 20100181604Abstract: A method of forming a sensor array. The method includes depositing a source/drain contact layer; depositing a semiconductor layer on the source/drain contact layer; and patterning the source/drain contact layer and the semiconductor layer substantially simultaneously, wherein the patterned semiconductor layer forms part of a sensor of the sensor array.Type: ApplicationFiled: January 22, 2010Publication date: July 22, 2010Applicant: PALO ALTO RESEARCH CENTER INCORPORATEDInventors: Sanjiv Sambandan, William S. Wong, Rene A. Lujan, Scott J. Limb
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Publication number: 20100158548Abstract: A system, including an improved sensor, for determining toner particle uniformity is described. The sensor measures toner particle charge, typically be having the charge on the toner particle control a current flow through the channel of a thin film transistor. By measuring the charge on many toner particles, the system determines whether sufficient toner degradation has occurred that the toner should be replaced. The sensor is particularly suitable for being formed on a thin diagnostic sheet that is input through the paper path of a printing system.Type: ApplicationFiled: December 18, 2008Publication date: June 24, 2010Applicant: Palo Alto Research Center IncorporatedInventors: William S. Wong, Michael L. Chabinyc, Sanjiv Sambandan, Pengfei Qi
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Patent number: 7742090Abstract: A method of making a curved sensor is described. The method involves projecting portions of a curved three dimensional structure such as a hemisphere onto a two dimensional substrate in an outline pattern. The outline pattern typically serves as a perimeter of a sensor. After forming a sensor in the shape of the outline pattern, the two dimensional substrate is flexed to form a three dimensional sensor structure.Type: GrantFiled: December 22, 2006Date of Patent: June 22, 2010Assignee: Palo Alto Research Center IncorporatedInventors: Robert A. Street, Sanjiv Sambandan, Jeng Ping Lu
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Publication number: 20100073530Abstract: A method and apparatus for using TFT transistors or MIS capacitors as light-sensing elements in charge mapping arrays. A bias stress may be applied to a plurality of pixels in a charge map array. As a result, charge carriers may be trapped in each of the plurality of pixels responsive to the bias stress, which may be observed as a value shift such as a threshold voltage VT shift. Light may then be transmitted toward the plurality of pixels in the charge map array causing some of the pixels to absorb the light. The trapped charge carriers are released in the pixels that absorbed the light and not released in the pixels that did not absorb the light. The value shift in each of the pixels can be compared to determine which of the pixels absorbed the light.Type: ApplicationFiled: September 22, 2008Publication date: March 25, 2010Applicant: PALO ALTO RESEARCH CENTER INCORPORATEDInventors: Tse Nga Ng, Sanjiv Sambandan, William S. Wong
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Publication number: 20100068856Abstract: A memory cell array including a data line; a capacitor; and a transistor coupled between the data line and the capacitor. At least one of the capacitor and the transistor includes a material with a mutable electrical characteristic. A memory cell array including a first transistor coupled between a first node, a second node, and a third node; and a second transistor coupled between the second node and a fourth node. The first transistor includes a material with a mutable electrical characteristic.Type: ApplicationFiled: November 19, 2009Publication date: March 18, 2010Applicant: PALO ALTO RESEARCH CENTER INCORPORATEDInventors: William S. Wong, Sanjiv Sambandan, Tse Nga Ng, Robert A. Street
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Publication number: 20100067280Abstract: A memory cell array including a data line; a capacitor; and a transistor coupled between the data line and the capacitor. At least one of the capacitor and the transistor includes a material with a mutable electrical characteristic. A memory cell array including a first transistor coupled between a first node, a second node, and a third node; and a second transistor coupled between the second node and a fourth node. The first transistor includes a material with a mutable electrical characteristic.Type: ApplicationFiled: November 19, 2009Publication date: March 18, 2010Applicant: PALO ALTO RESEARCH CENTER INCORPORATEDInventors: William S. Wong, Sanjiv Sambandan, Tse Nga Ng, Robert A. Street
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Publication number: 20100067316Abstract: A memory cell array including a data line; a capacitor; and a transistor coupled between the data line and the capacitor. At least one of the capacitor and the transistor includes a material with a mutable electrical characteristic. A memory cell array including a first transistor coupled between a first node, a second node, and a third node; and a second transistor coupled between the second node and a fourth node. The first transistor includes a material with a mutable electrical characteristic.Type: ApplicationFiled: November 19, 2009Publication date: March 18, 2010Applicant: PALO ALTO RESEARCH CENTER INCORPORATEDInventors: William S. Wong, Sanjiv Sambandan, Tse Nga Ng, Robert A. Street
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Patent number: 7679951Abstract: A memory cell array including a data line; a capacitor; and a transistor coupled between the data line and the capacitor. At least one of the capacitor and the transistor includes a material with a mutable electrical characteristic. A memory cell array including a first transistor coupled between a first node, a second node, and a third node; and a second transistor coupled between the second node and a fourth node. The first transistor includes a material with a mutable electrical characteristic.Type: GrantFiled: December 21, 2007Date of Patent: March 16, 2010Assignee: Palo Alto Research Center IncorporatedInventors: William S. Wong, Sanjiv Sambandan, Tse Nga Ng, Robert A. Street
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Publication number: 20100060560Abstract: A pixel circuit including a first transistor; a second transistor, the first transistor and the second transistor serially coupled between a first power supply terminal and a second power supply terminal; and a first capacitor coupled between a gate of the first transistor and a gate of the second transistor, and an electronic sheet including the same.Type: ApplicationFiled: September 8, 2008Publication date: March 11, 2010Applicant: PALO ALTO RESEARCH CENTER INCORPORATEDInventors: SANJIV SAMBANDAN, WILLIAM S. WONG, ROBERT A. STREET