Abstract: Antibody drug conjugates (ADCs) comprising an antibody conjugated to an anti-inflammatory therapeutic agent via a phosphate-based linker with tunable extracellular and intracellular stability are described.

Abstract: Antibody drug conjugates (ADCs) comprising an antibody conjugated to an anti-inflammatory therapeutic agent via a phosphate-based linker with tunable extracellular and intracellular stability are described.

Abstract: Various implementations include wearable audio devices having a spatialized virtual personal assistant (VPA). In other implementations, a method of controlling a wearable audio device having a spatialized VPA is disclosed. Other implementations include a method of generating a spatialized VPA in a wearable audio device.

Abstract: Antibody drug conjugates (ADCs) comprising an antibody conjugated to an anti-inflammatory therapeutic agent via a phosphate-based linker with tunable extracellular and intracellular stability are described.

Abstract: Various implementations include wearable audio devices having a spatialized virtual personal assistant (VPA). In other implementations, a method of controlling a wearable audio device having a spatialized VPA is disclosed. Other implementations include a method of generating a spatialized VPA in a wearable audio device.

Abstract: Phosphate-based linkers with tunable stability for intracellular delivery of drug conjugates are described. The phosphate-based linkers comprise a monophosphate, diphosphate, triphosphate, or tetraphosphate group (phosphate group) and a linker arm comprising a tuning element and optionally a spacer. A payload is covalently linked to the phosphate group at the distal end of the linker arm and the functional group at the proximal end of the linker arm is covalently linked to a cell-specific targeting ligand such as an antibody. These phosphate-based linkers have a differentiated and tunable stability in blood vs. an intracellular environment (e.g. lysosomal compartment).

Abstract: Phosphate-based linkers with tunable stability for intracellular delivery of drug conjugates are described. The phosphate-based linkers comprise a monophosphate, diphosphate, triphosphate, or tetraphosphate group (phosphate group) and a linker arm comprising a tuning element and optionally a spacer. A payload is covalently linked to the phosphate group at the distal end of the linker arm and the functional group at the proximal end of the linker arm is covalently linked to a cell-specific targeting ligand such as an antibody. These phosphate-based linkers have a differentiated and tunable stability in blood vs. an intracellular environment (e.g. lysosomal compartment).

Abstract: A first execution time of a first thread executing on a first processing unit of a multiprocessor is determined. A second execution time of a second thread executing on a second processing unit of the multiprocessor is determined, the first and second threads executing in parallel. Power is set to the first and second processing units to effectuate the first and second threads to finish executing at approximately the same time in future executions of the first and second threads. Other embodiments are also described and claimed.

Abstract: Method, apparatus and system embodiments to schedule user-level OS-independent “shreds” without intervention of an operating system. For at least one embodiment, the shred is scheduled for execution by a scheduler routine rather than the operating system. The scheduler routine may receive compiler-generated hints from a compiler. The compiler hints may be generated by the compiler without user-provided pragmas, and may be passed to the scheduler routine via an API-like interface. The interface may include a scheduling hint data structure that is maintained by the compiler. Other embodiments are also described and claimed.

Abstract: A first execution time of a first thread executing on a first processing unit of a multiprocessor is determined. A second execution time of a second thread executing on a second processing unit of the multiprocessor is determined, the first and second threads executing in parallel. Power is set to the first and second processing units to effectuate the first and second threads to finish executing at approximately the same time in future executions of the first and second threads. Other embodiments are also described and claimed.

Abstract: A first execution time of a first thread executing on a first processing unit of a multiprocessor is determined. A second execution time of a second thread executing on a second processing unit of the multiprocessor is determined, the first and second threads executing in parallel. Power is set to the first and second processing units to effectuate the first and second threads to finish executing at approximately the same time in future executions of the first and second threads. Other embodiments are also described and claimed.

Abstract: A method for improving parallel processing of computer programs. DOACROSS loops and similar code are identified and parallelized using a post-wait control structure. The post-wait control structure may be implemented to include any one of a single counter to enforce an order of execution, an array to track code completion that is indexed by a modulus of a positive integer number, and/or a set of arrays to track a last code completed by a thread and a current code being executed by a thread.

Abstract: An approach is provided for automating workflow. A sales order is received. One of a plurality of implementation centers is selected based on a rule. The sales order is stored in one of a plurality of queues that are mapped to the implementation centers.

Abstract: Methods and apparatus for reducing memory latency in a software application are disclosed. A disclosed system uses one or more helper threads to prefetch variables for a main thread to reduce performance bottlenecks due to memory latency and/or a cache miss. A performance analysis tool is used to profile the software application's resource usage and identifies areas in the software application experiencing performance bottlenecks. Compiler-runtime instructions are generated into the software application to create and manage the helper thread. The helper thread prefetches data in the identified areas of the software application experiencing performance bottlenecks. A counting mechanism is inserted into the helper thread and a counting mechanism is inserted into the main thread to coordinate the execution of the helper thread with the main thread and to help ensure the prefetched data is not removed from the cache before the main thread is able to take advantage of the prefetched data.

Abstract: A method for improving parallel processing of computer programs. DOACROSS loops and similar code are identified and parallelized using a post-wait control structure. The post-wait control structure may be implemented to include any one of a single counter to enforce an order of execution, an array to track code completion that is indexed by a modulus of a positive integer number, and/or a set of arrays to track a last code completed by a thread and a current code being executed by a thread.

Abstract: A first execution time of a first thread executing on a first processing unit of a multiprocessor is determined. A second execution time of a second thread executing on a second processing unit of the multiprocessor is determined, the first and second threads executing in parallel. Power is set to the first and second processing units to effectuate the first and second threads to finish executing at approximately the same time in future executions of the first and second threads. Other embodiments are also described and claimed.

Abstract: Data structure creation, organization and management techniques for data local to user-level threads are provided. Other embodiments are also described and claimed.

Abstract: Method, apparatus and system embodiments to schedule user-level OS-independent “shreds” without intervention of an operating system. For at least one embodiment, the shred is scheduled for execution by a scheduler routine rather than the operating system. The scheduler routine may receive compiler-generated hints from a compiler. The compiler hints may be generated by the compiler without user-provided pragmas, and may be passed to the scheduler routine via an API-like interface. The interface may include a scheduling hint data structure that is maintained by the compiler. Other embodiments are also described and claimed.

Abstract: Method, apparatus and system embodiments to schedule user-level OS-independent “shreds” without intervention of an operating system. For at least one embodiment, the shred is scheduled for execution by a scheduler routine rather than the operating system. The scheduler routine resides in user space and may be part of a runtime library. The library may also include monitoring logic that monitors execution of a shredded program and provides scheduling hints, based on shred dependence information, to the scheduler. In addition, the scheduler may further optimize shred scheduling by taking into account information about a system's configuration of thread execution hardware. Other embodiments are also described and claimed.

Abstract: A technique to monitor software thread performance and update software that issues or uses the thread(s) to reduce performance-inhibiting events. At least one embodiment of the invention uses hardware and/or software timers or counters to monitor various events associated with executing user-level threads and report these events back to a user-level software program, which can use the information to avoid or at least reduce performance-inhibiting events associated with the user-level threads.