Abstract: A method includes obtaining patient medical record information from a plurality of providers until a demographic profile of patients associated with the patient medical record information meets a desired demographic profile; querying the patient medical record information using selection criteria to identify a first subset of patients having first characteristics that match first screening requirements for a clinical trial; identifying, using an artificial intelligence engine, ones of the first subset of patients whose medical record information includes second characteristics that match second screening requirements for the clinical trial as clinical trial patient candidates; and communicating identities of the clinical trial patient candidates to ones of the plurality of providers that provide healthcare services to the clinical trial patient candidates, respectively. The plurality of providers are associated with a plurality of different organizational managing entities, respectively.

Abstract: A method includes receiving patient medical record information from each of a plurality of providers, the plurality of providers being associated with a plurality of different organizational managing entities, respectively; querying the patient medical record information of each of the plurality of providers using selection criteria to identify a first subset patients having first characteristics that match first screening requirements for a clinical trial; identifying, using an artificial intelligence engine, ones of the first subset of patients whose medical record information includes second characteristics that match second screening requirements for the clinical trial as clinical trial patient candidates; and communicating identities of the clinical trial patient candidates to ones of the plurality of providers that provide healthcare services to the clinical trial patient candidates, respectively.

Abstract: In one embodiment, a processor includes at least one core and an interface circuit to interface the at least one core to additional circuitry of the processor. In response to an in-field self test instruction, at least one core may save state to a low power memory, enter into a diagnostic sleep state and execute an in-field self test in the diagnostic sleep state in which the at least one core appears to be inactive. Other embodiments are described and claimed.

Abstract: In one embodiment, a processor includes at least one core and an interface circuit to interface the at least one core to additional circuitry of the processor. In response to an in-field self test instruction, at least one core may save state to a low power memory, enter into a diagnostic sleep state and execute an in-field self test in the diagnostic sleep state in which the at least one core appears to be inactive. Other embodiments are described and claimed.

Abstract: In one embodiment, a processor includes at least one core and an interface circuit to interface the at least one core to additional circuitry of the processor. In response to an in-field self test instruction, at least one core may save state to a low power memory, enter into a diagnostic sleep state and execute an in-field self test in the diagnostic sleep state in which the at least one core appears to be inactive. Other embodiments are described and claimed.

Abstract: In one embodiment, a processor includes at least one core and an interface circuit to interface the at least one core to additional circuitry of the processor. In response to an in-field self test instruction, at least one core may save state to a low power memory, enter into a diagnostic sleep state and execute an in-field self test in the diagnostic sleep state in which the at least one core appears to be inactive. Other embodiments are described and claimed.

Abstract: A technique to promote determinism among multiple clocking domains within a computer system or integrated circuit, In one embodiment, one or more execution units are placed in a deterministic state with respect to multiple clocks within a processor system having a number of different clocking domains.

Abstract: A technique to promote determinism among multiple clocking domains within a computer system or integrated circuit, In one embodiment, one or more execution units are placed in a deterministic state with respect to multiple clocks within a processor system having a number of different clocking domains.

Abstract: A method and apparatus if described herein for accessing a physical memory location referenced by a physical address with a processor. The processor fetches/receives instructions with references to virtual memory addresses and/or references to physical addresses. Translation logic translates the virtual memory addresses to physical addresses and provides the physical addresses to a common interface. Physical addressing logic decodes references to physical addresses and provides the physical addresses to a common interface based on a memory type stored by the physical addressing logic.

Abstract: In one embodiment of the present invention, a method includes switching between a first address space and a second address space, determining if the second address space exists in a list of address spaces; and maintaining entries of the first address space in a translation buffer after the switching. In such manner, overhead associated with such a context switch may be reduced.

Abstract: In one embodiment, information pertaining to a first fault occurring during operation of a virtual machine (VM) is stored in a first field. A second fault is detected while delivering the first fault to the VM, and a determination is made as to whether the second fault is associated with a transition of control to a virtual machine monitor (VMM). If this determination is positive, information pertaining to the second fault is stored in a second field, and control is transitioned to the VMM.

Abstract: A virtual machine extension (VMX) architecture. More particularly, embodiments of the invention relate to improving the performance of execution of VMREAD and VMWRITE instructions.

Abstract: A virtual machine extension (VMX) architecture. More particularly, embodiments of the invention relate to a method and apparatus to enable single stepping of a guest application within a microprocessor or group of processing elements.

Abstract: In one embodiment, a method includes receiving a request to transition control to a virtual machine (VM) from a virtual machine monitor (VMM), determining that a single-stepping indicator is set to a single stepping value, and transitioning control to the VM. Further, if an execution of a first instruction in the VM completes successfully, control is transitioned to the VMM following the successful completion of the execution of the first instruction.