Abstract: In described examples, a latch includes circuitry for latching input information. The circuitry can be precharged in response to an indication of a first mode and can latch the input information to an indication of a second mode. The latch can optionally further latch the input information in response to a node for storing the latched input information.

Abstract: In described examples, a latch includes circuitry for latching input information. The circuitry can be precharged in response to an indication of a first mode and can latch the input information to an indication of a second mode. The latch can optionally further latch the input information in response to a node for storing the latched input information.

Abstract: A global navigation satellite system (GNSS) includes an efficient memory sharing architecture that provides additional search capacity by, e.g., sharing a portion of GNSS receiver processor memory with a general processor. A memory management unit dynamically revectors memory accesses in accordance with the various states of the GNSS receiver processor and arranging the available memory as a shared memory bank that can be efficiently shared between the general processor and the GNSS receiver processor. An optional ancillary memory system can provide additional memory to the general processor when the GNSS receiver processor has allocated memory that the general processor would otherwise use.

Abstract: A global navigation satellite system (GNSS) includes an efficient memory sharing architecture that provides additional search capacity by, e.g., sharing a portion of GNSS receiver processor memory with a general processor. A memory management unit dynamically revectors memory accesses in accordance with the various states of the GNSS receiver processor and arranging the available memory as a shared memory bank that can be efficiently shared between the general processor and the GNSS receiver processor. An optional ancillary memory system can provide additional memory to the general processor when the GNSS receiver processor has allocated memory that the general processor would otherwise use.

Abstract: An apparatus and method for reducing interference signals using multiphase clocks. An integrated circuit includes a digital circuit and an analog circuit. The digital circuit includes a derived clock circuit configured to receive a root clock having a frequency D*f, D being a divide factor, to divide the root clock by D, and generate multiphase clocks having N phases. N circuits of the digital circuit are configured to receive a corresponding one of the N phases, with edges of the multiphase clocks being spread over the N phases. The multiphase clocks cause a frequency shift in interference signals generated by reduced periodic peak currents drawn by the N circuits from f to N*f and harmonics thereof. The analog circuit receives an in-band range of signals. A value of N is configured to shift the interference signals outside the in-band range of signals.

Abstract: A networking device (810) includes user interface circuitry (838) operable for user input and display, a host processor (880) coupled with the user interface circuits (838); a network modem (870) and a peripheral interface processor (810) coupled with the host processor (880) and operable to automatically execute content receptions and transmission through the network modem (870) at least sometimes independently of the user interface circuits (838) and the host processor (880); and a local content storage (820) coupled with the peripheral interface processor (810) and wherein the peripheral interface processor (810) is operable with the modem (870) to transmit trigger signals representing controls to pull remote content from elsewhere and to subsequently receive such content via the modem (870) for the local content storage (820). Other network circuits, devices, systems and processes and peripheral interface circuits, devices, systems and processes are also disclosed.

Abstract: An apparatus and method for reducing interference signals using multiphase clocks. An integrated circuit includes a digital circuit and an analog circuit. The digital circuit includes a derived clock circuit configured to receive a root clock having a frequency D*f, D being a divide factor, to divide the root clock by D, and generate multiphase clocks having N phases. N circuits of the digital circuit are configured to receive a corresponding one of the N phases, with edges of the multiphase clocks being spread over the N phases. The multiphase clocks cause a frequency shift in interference signals generated by reduced periodic peak currents drawn by the N circuits from f to N*f and harmonics thereof. The analog circuit receives an in-band range of signals. A value of N is configured to shift the interference signals outside the in-band range of signals.