Patents by Inventor Sankara Narayanan Ekkanath Madathil
Sankara Narayanan Ekkanath Madathil has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9087889Abstract: A semiconductor device comprises three semiconductor layers. The semiconductor layers are arranged to form a 2DHG and a 2DEG separated by a polarization layer. The device comprises a plurality of electrodes: first and second electrodes electrically connected to the 2DHG so that current can flow between them via the 2DHG and a third electrode electrically connected to the 2DEG so that when a positive voltage is applied to the third electrode, with respect to at least one of the other electrodes, the 2DEG and the 2DHG will be at least partially depleted.Type: GrantFiled: June 7, 2011Date of Patent: July 21, 2015Assignee: The University of SheffieldInventors: Akira Nakajima, Sankara Narayanan Ekkanath Madathil
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Patent number: 8785976Abstract: A low-loss GaN-based semiconductor device is provided. The semiconductor device has the InzGa1-zN layer (where 0?z<1), the AlxGa1-xN layer (where 0<x<1), the InyGa1-yN layer (where 0?y<1) and the p-type InwGa1-wN layer (where 0?w<1) which are sequentially stacked on a base substrate of a C-plane sapphire substrate, etc. At a non-operating time, the two-dimensional hole gas is formed in the InyGa1-yN layer in the vicinity part of a hetero-interface between the AlxGa1-xN layer and the InyGa1-yN layer, and the two-dimensional electron gas is formed in the InzGa1-zN layer in the vicinity part of a hetero-interface between the InzGa1-zN layer and the AlxGa1-xN layer.Type: GrantFiled: June 21, 2011Date of Patent: July 22, 2014Assignees: The University of Sheffield, Powdec K.K.Inventors: Akira Nakajima, Sankara Narayanan Ekkanath Madathil, Yasunobu Sumida, Hiroji Kawai
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Publication number: 20130221409Abstract: A semiconductor device comprises three semiconductor layers. The semiconductor layers are arranged to form a 2DHG and a 2DEG separated by a polarization layer. The device comprises a plurality of electrodes: first and second electrodes electrically connected to the 2DHG so that current can flow between them via the 2DHG and a third electrode electrically connected to the 2DEG so that when a positive voltage is applied to the third electrode, with respect to at least one of the other electrodes, the 2DEG and the 2DHG will be at least partially depleted.Type: ApplicationFiled: June 7, 2011Publication date: August 29, 2013Applicant: THE UNIVERSITY OF SHEFFIELDInventors: Akira Nakajima, Sankara Narayanan Ekkanath Madathil
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Publication number: 20130126942Abstract: A low-loss GaN-based semiconductor device is provided. The semiconductor device has the InzGa1-zN layer (where 0?z<1), the AlxGa1-xN layer (where 0<x<1), the InyGa1-yN layer (where 0?y<1) and the p-type InwGa1-wN layer (where 0?w<1) which are sequentially stacked on a base substrate of a C-plane sapphire substrate, etc. At a non-operating time, the two-dimensional hole gas 15 is formed in the InyGa1-yN layer in the vicinity part of a hetero-interface between the AlxGa1-xN layer and the InyGa1-yN layer, and the two-dimensional electron gases is formed in the InzGa1-zN layer in the vicinity part of a hetero-interface between the InzGa1-zN layer and the AlxGa1-xN layer.Type: ApplicationFiled: June 21, 2011Publication date: May 23, 2013Applicants: POWDEC K.K., THE UNIVERSITY OF SHEFFIELDInventors: Akira Nakajima, Sankara Narayanan Ekkanath Madathil, Yasunobu Sumida, Hiroji Kawai
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Patent number: 7893457Abstract: A semiconductor device includes at least one cell including a base region of a first conductivity type having disposed therein at least one emitter region of a second conductivity type, a first well region of a second conductivity type, a second well region of a first conductivity type, a drift region of a second conductivity type, a collector region of a first conductivity type, and a collector contact. Each cell is disposed within the first well region, and the first well region is disposed within the second well region. The device further includes a first gate in communication with a base region so that a MOSFET channel can be formed between an emitter region and the first well region, and at least one embedded region embedded in the first well region. The device is configured such that during operation of the device a depletion region at a junction between the base region and the first well region can extend to a junction between the first well region and the second well region.Type: GrantFiled: August 10, 2005Date of Patent: February 22, 2011Assignee: ECO Semiconductors Ltd.Inventors: Sankara Narayanan Ekkanath Madathil, Mark Robert Sweet, Konstantin Vladislavovich Vershinin
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Publication number: 20090159928Abstract: A power semiconductor device including source and drain regions located in a lateral arrangement in a first portion of the device, and at least one current providing cell located in a second portion of the device and spaced apart from the first portion at least by a substrate region of a first conductivity type.Type: ApplicationFiled: October 16, 2006Publication date: June 25, 2009Applicant: ECO SEMICONDUCTORS LTDInventors: Sankara Narayanan Ekkanath Madathil, David William Green
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Publication number: 20080191238Abstract: According to the invention there is provided a semiconductor device including: at least one cell including a base region of a first conductivity type having disposed therein at least one emitter region of a second conductivity type; a first well region of a second conductivity type; a second well region of a first conductivity type; a drift region of a second conductivity type; a collector region of a first conductivity type; a collector contact; in which each cell is disposed within the first well region and the first well region is disposed within the second well region; the device further including: a first gate in communication with a base region so that a MOSFET channel can be formed between an emitter region and the first well region; and at least one embedded region embedded in the first well region; in which the device is configured such that during operation of the device a depletion region at a junction between the base region and the first well region can extend to a junction between the first wellType: ApplicationFiled: August 10, 2005Publication date: August 14, 2008Applicant: ECO SEMICONDUCTORS LIMITEDInventors: Sankara Narayanan Ekkanath Madathil, Mark Robert Sweet, Konstantin Vladislavovich Vershinin
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Patent number: 6724043Abstract: There is disclosed a semiconductor device comprising: at least one cell comprising a base region (32) of a first conductivity type having disposed therein at least one emitter region (36a, 36b) of a second conductivity type; a first well region (22) of a second conductivity type; a second well region (2a) of a first conductivity type; a drift region (24) of a second conductivity type; a collector region (14) of a first conductivity type; a collector contact (16) in which each cell is disposed within the first well region (22) and the first well region (22) is disposed within the second well-region (20); the device further comprising: a first gate (61) disposed over a base region (32) so that a MOSFET channel can be formed between an emitter region (36a, 36b) and the first well region (22); the device further comprising: a second gate disposer over the second well region (20) so that a MOSFET channel can be formed between the first well region (22) and the drift region (24).Type: GrantFiled: August 22, 2002Date of Patent: April 20, 2004Assignee: De Montfort UniversityInventor: Sankara Narayanan Ekkanath Madathil