Abstract: According to the embodiment discloses a method providing direct RF sampling of the received signal in a full duplex system. A sampler in the full-duplex system comprises a buffer to clip an amplitude information from each of a coupled transmitter (Tx) signal and a voltage at an antenna port of the sampler for obtaining a buffered transmitter signal and a buffered voltage at the antenna port. Phase detector in the sampler is configured to perform sampling of time delay between the buffered transmitter signal and the voltage at the antenna port and generate an output. The sampler further comprises current integrator configured to pass the output of the phase detector for generating a sampled output, wherein the sampled output generates an output received signal.

Abstract: Embodiments herein provide a transceiver system 1000a-1000f for full-duplex communication. The transceiver system 1000a-1000f includes an electrical balance based duplexer (EBD) 100 coupled with at least one transceiver 200a and 200b and at least one antenna 300a and 300b. The at least one antenna 300a and 300b is configured to transmit first signals and the at least one antennas 300a and 300b is configured to receive second signals using at least one circulators. The EBD 100 is configured to provide an isolation between the transmitting signals and the receiving signals in a same channel full duplex (SCFD) front-end circuit using the at least one circulators.

Abstract: According to the embodiment discloses a method providing direct RF sampling of the received signal in a full duplex system. A sampler in the full-duplex system comprises a buffer to clip an amplitude information from each of a coupled transmitter (Tx) signal and a voltage at an antenna port of the sampler for obtaining a buffered transmitter signal and a buffered voltage at the antenna port. Phase detector in the sampler is configured to perform sampling of time delay between the buffered transmitter signal and the voltage at the antenna port and generate an output. The sampler further comprises current integrator configured to pass the output of the phase detector for generating a sampled output, wherein the sampled output generates an output received signal.

Abstract: Embodiments herein provide a transceiver system 1000a-1000f for full-duplex communication. The transceiver system 1000a-1000f includes an electrical balance based duplexer (EBD) 100 coupled with at least one transceiver 200a and 200b and at least one antenna 300a and 300b. The at least one antenna 300a and 300b is configured to transmit first signals and the at least one antennas 300a and 300b is configured to receive second signals using at least one circulators. The EBD 100 is configured to provide an isolation between the transmitting signals and the receiving signals in a same channel full duplex (SCFD) front-end circuit using the at least one circulators.

Abstract: Described examples include circuitry and methods to control lock time of a phase lock loop (PLL) or other locking circuit, in which a phase frequency detector (PFD) circuit is switched from a first mode to provide a control input signal to a charge pump as a pulse signal having a pulse width corresponding to a phase difference between a reference clock signal and a feedback clock signal to a second mode to hold the control input signal at a constant value for a predetermined time in response to detected cycle slip conditions to enhance loop filter current during frequency transitions to reduce lock time for the locking circuit.

Abstract: Described examples include circuitry and methods to control lock time of a phase lock loop (PLL) or other locking circuit, in which a phase frequency detector (PFD) circuit is switched from a first mode to provide a control input signal to a charge pump as a pulse signal having a pulse width corresponding to a phase difference between a reference clock signal and a feedback clock signal to a second mode to hold the control input signal at a constant value for a predetermined time in response to detected cycle slip conditions to enhance loop filter current during frequency transitions to reduce lock time for the locking circuit.

Abstract: Selectable sizes for a local oscillator (LO) buffer and mixer are disclosed. In an exemplary embodiment, LO buffer and/or mixer size may be increased when a receiver or transmitter operates in a high gain mode, while LO buffer and/or mixer size may be decreased when the receiver or transmitter operates in a low gain mode. In an exemplary embodiment, LO buffer and mixer sizes are increased and decreased in lock step. Circuit topologies and control schemes for specific exemplary embodiments of LO buffers and mixers having adjustable size are disclosed.

Abstract: A frequency synthesizer circuit is disclosed. The frequency synthesizer circuit includes a phase and frequency detector. The frequency synthesizer circuit also includes a first charge pump and a second charge pump, each coupled to the phase and frequency detector. The frequency synthesizer circuit also includes a loop filter that includes a resistor and at least two capacitors. The second charge pump is coupled between the resistor and a capacitor that creates a zero in a transfer function of the loop filter. The frequency synthesizer circuit also includes a voltage controlled oscillator that produces an output frequency based on an output of the loop filter.

Abstract: Method and apparatus for configuring a transmitter circuit to support linear or polar mode. In the linear mode, a baseband signal is specified by adjusting the amplitudes of in-phase (I) and quadrature (Q) signals, while in the polar mode, the information signal is specified by adjusting the phase of a local oscillator (LO) signal and the amplitude of either an I or a Q signal. In an exemplary embodiment, two mixers are provided for both linear and polar mode, with a set of switches selecting the appropriate input signals provided to one of the mixers based on whether the device is operating in linear or polar mode. In an exemplary embodiment, each mixer may be implemented using a scalable architecture that efficiently adjusts mixer size based on required transmit power.

Abstract: Techniques are provided for dynamically biasing an amplifier to extend the amplifier's operating range while conserving power. In an embodiment, a detector is provided to measure the amplifier output to determine an operating region of the amplifier. The output of the detector may be input to a bias adjuster, which outputs a dynamic voltage level supplied to at least one bias transistor in the amplifier. Multiple embodiments of the detector and bias adjuster are disclosed.

Abstract: A frequency synthesizer circuit is disclosed. The frequency synthesizer circuit includes a phase and frequency detector. The frequency synthesizer circuit also includes a first charge pump and a second charge pump, each coupled to the phase and frequency detector. The frequency synthesizer circuit also includes a loop filter that includes a resistor and at least two capacitors. The second charge pump is coupled between the resistor and a capacitor that creates a zero in a transfer function of the loop filter. The frequency synthesizer circuit also includes a voltage controlled oscillator that produces an output frequency based on an output of the loop filter.

Abstract: Method and apparatus for configuring a transmitter circuit to support multiple modes and/or frequency bands. In an embodiment, a pre-driver amplifier (pDA) in a transmit (TX) signal path is selectively bypassed by a controllable switch. The switch can be controlled based on a mode of operation of the transmitter circuit. Further techniques are disclosed for selectively coupling the output of a driver amplifier (DA) to at least one of a plurality of off-chip connections, each connection coupling the DA output to a set of off-chip components.

Abstract: Techniques are disclosed for extending an amplifier's linear operating range by concatenating an amplifier exhibiting gain compression with a gain expansion stage. In an exemplary embodiment, a gain expansion stage incorporates a Class-B stage, a Class-AB stage, or a combination of the two. In an exemplary embodiment, both the gain compression stage and gain expansion stage are provided with a replica current biasing scheme to ensure stable biasing current over variations in temperature, process, and/or supply voltage. Further disclosed is an output voltage biasing scheme to set the DC output voltage to ensure maximum linear operating range.

Abstract: A method an apparatus for synchronizing phases of one or more divider units comprise powering on a master divider unit to provide a reference signal. A phase of a slave divider unit is synchronized to the reference signal from the master divider unit by providing a power on pulse at the slave divider unit, synchronizing the phase of the slave divider unit to the reference signal using a digitally controlled oscillator, and powering on the slave divider unit after a first predetermined delay period following a rising edge of the power on pulse. By synchronizing a slave divider unit to the reference signal from the master divider unit, any number of slave divider units may be powered on and in-phase with each other.

Abstract: A circuit receives a first signal (for example, a baseband signal) and mixes it with a local oscillator (LO) signal, and outputs a second signal (for example, an RFOUT signal). The circuit includes multiple identical Mixer and Frequency Divider Pair (MFDP) circuits. Each MFDP can be enabled separately. Each MFDP includes a mixer and a frequency divider that provides the mixer with a local version of the LO signal. The MFDP outputs are coupled together so that the output power of the second signal (RFOUT) is the combined output powers of the various MFDPs. By controlling the number of enabled MFDPs, the output power of the second signal is controlled. Because the MFDPs all have identical layouts, accuracy of output power step size is improved. Because LO signal power within the circuit automatically changes in proportion to the number of enabled MFDPs, local oscillator leakage problems are avoided.

Abstract: Techniques for improving the quality factor (“Q”) of a balun in the presence of loading stages are disclosed. In an exemplary embodiment, the ground node of a balun secondary (single-ended) element is connected to a source node of an amplifier stage via a common ground node. The connection may be made physically short to minimize any parasitic elements. In another exemplary embodiment, the common ground node may be coupled to an off-chip ground voltage via a peaking inductor. The peaking inductor may be implemented on-chip, e.g., as a spiral inductor, or off-chip e.g., using bondwires.

Abstract: Techniques for improving the quality factor (“Q”) of a balun in the presence of loading stages are disclosed. In an exemplary embodiment, the ground node of a balun secondary (single-ended) element is connected to a source node of an amplifier stage via a common ground node. The connection may be made physically short to minimize any parasitic elements. In another exemplary embodiment, the common ground node may be coupled to an off-chip ground voltage via a peaking inductor. The peaking inductor may be implemented on-chip, e.g., as a spiral inductor, or off-chip e.g., using bondwires.

Abstract: Method and apparatus for configuring a transmitter circuit to support multiple modes and/or frequency bands. In an embodiment, a pre-driver amplifier (pDA) in a transmit (TX) signal path is selectively bypassed by a controllable switch. The switch can be controlled based on a mode of operation of the transmitter circuit. Further techniques are disclosed for selectively coupling the output of a driver amplifier (DA) to at least one of a plurality of off-chip connections, each connection coupling the DA output to a set of off-chip components.

Abstract: Techniques are disclosed for extending an amplifier's linear operating range by concatenating an amplifier exhibiting gain compression with a gain expansion stage. In an exemplary embodiment, a gain expansion stage incorporates a Class-B stage, a Class-AB stage, or a combination of the two. In an exemplary embodiment, both the gain compression stage and gain expansion stage are provided with a replica current biasing scheme to ensure stable biasing current over variations in temperature, process, and/or supply voltage. Further disclosed is an output voltage biasing scheme to set the DC output voltage to ensure maximum linear operating range.

Abstract: A method an apparatus for synchronizing phases of one or more divider units comprise powering on a master divider unit to provide a reference signal. A phase of a slave divider unit is synchronized to the reference signal from the master divider unit by providing a power on pulse at the slave divider unit, synchronizing the phase of the slave divider unit to the reference signal using a digitally controlled oscillator, and powering on the slave divider unit after a first predetermined delay period following a rising edge of the power on pulse. By synchronizing a slave divider unit to the reference signal from the master divider unit, any number of slave divider units may be powered on and in-phase with each other.