Patents by Inventor Sankaran Menon
Sankaran Menon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240103077Abstract: Time to read the data registers in a remote Test Access Port (TAP) in a subsystem in a System-on-Chip (SoC) is reduced by reading multiple data registers in remote Test Access Ports in parallel. A Test Access Port Bridge provides access to multiple same width data registers in parallel. The same width data registers can be for the same function or different functions. The subsystems with a remote Test Access Port in the SoC can include Peripheral Component Interconnect Express (PCIe), Voltage Droop Monitors (VDMs), In-Die Variation (IDV) Monitor fub-lets, Temperature Sensors, Performance Monitors and telemetry subsystems.Type: ApplicationFiled: September 28, 2022Publication date: March 28, 2024Inventors: Rakesh KANDULA, Sankaran MENON, Rolf KUEHNIS
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Publication number: 20240103079Abstract: Embodiments described herein may include apparatus, systems, techniques, and/or processes that are directed to performing testing of a device while a system is operational. A device may include computing circuitry and host connectivity registers. Host connectivity registers contain configuration and memory mapping data programmed by system software upon power up of the device and computing system. The data contained in host connectivity registers should be always maintained while the computing system is operational. Scan test circuitry may be implemented, providing the ability to test the device while the system is operational. Preservation circuitry preserves or maintains the data stored in host connectivity registers allowing in-operation testing of the device, ensuring the device the ability to return to full operation at the end of in-operation testing without requiring system software to reprogram the host connectivity registers.Type: ApplicationFiled: September 28, 2022Publication date: March 28, 2024Inventors: Rakesh Kandula, Sankaran Menon, Rolf Kuehnis
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Patent number: 11933843Abstract: An Automated Dynamic low voltage monitoring (LVM) based Low-Power (ADLLP) debug capability for a system-on-chip (SoC) as well as the open/closed-chassis platform for faster TTM (Time to Market) of the final platform or system. ADLLP Debug is achieved by detection of the probe connection between a target system (e.g., SoC) and debug host system. A user can dynamically override the power, clocks and LVM for intellectual property (IP) blocks not part of the debug trace by instructing a Power Management Controller (PMC) via the Inter Processor Communication (IPC) mailbox (or any other suitable mailbox driver) to set the registers in a Target Firmware (TFW) based on the probe and debug use-case.Type: GrantFiled: July 15, 2021Date of Patent: March 19, 2024Assignee: Intel CorporationInventors: Keith A. Jones, Wai Mun Ng, Thomas A. Lyda, Subinlal Pk, Sankaran Menon, Vui Yong Liew, Kristan K. Wiseley
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Publication number: 20230408581Abstract: Techniques for interface conversion and unicast for test content, firmware, and software delivery are described. An example apparatus comprises a scan test interface coupled to multiple circuits blocks to perform a scan test for the multiple circuit blocks, and circuitry coupled to input/output (IO) signals of the scan test interface to provide content for the multiple circuit blocks and to deliver a replicated content to multiple endpoints of the multiple circuit blocks (e.g., unicast technology). In another example, the circuitry is coupled to the IO signals of the scan test interface and a system/communication interface to decode packets received at the IO signals and convert the decoded packets to provide content through the system/communication interface for the multiple circuit blocks. Other examples are described and claimed.Type: ApplicationFiled: June 15, 2022Publication date: December 21, 2023Applicant: Intel CorporationInventors: Rakesh Kandula, Sankaran Menon, Seng Choon Thor, Shivaprashant Bulusu, Eswar Vadlamani, Ramakrishnan Venkatasubramanian
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Publication number: 20230195416Abstract: An integrated circuit is provided that includes via-configured structured logic circuitry and an embedded arithmetic block that interfaces with the via-configured structured logic circuitry to perform an arithmetic function. The embedded arithmetic block includes at least one monolithic arithmetic circuit that can perform the arithmetic function more efficiently or taking up less die space than a comparable circuit formed from the via-configured structured logic circuitry.Type: ApplicationFiled: December 22, 2021Publication date: June 22, 2023Inventors: Sankaran Menon, Martin Langhammer, Mustansir Fanaswalla, Kuldeep Simha
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Publication number: 20220018901Abstract: An Automated Dynamic low voltage monitoring (LVM) based Low-Power (ADLLP) debug capability for a system-on-chip (SoC) as well as the open/closed-chassis platform for faster TTM (Time to Market) of the final platform or system. ADLLP Debug is achieved by detection of the probe connection between a target system (e.g., SoC) and debug host system. A user can dynamically override the power, clocks and LVM for intellectual property (IP) blocks not part of the debug trace by instructing a Power Management Controller (PMC) via the Inter Processor Communication (IPC) mailbox (or any other suitable mailbox driver) to set the registers in a Target Firmware (TFW) based on the probe and debug use-case.Type: ApplicationFiled: July 15, 2021Publication date: January 20, 2022Inventors: Keith A. Jones, Wai Mun Ng, Thomas A. Lyda, Subinlal Pk, Sankaran Menon, Vui Yong Liew, Kristan K. Wiseley
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Patent number: 10733077Abstract: Techniques and apparatus for error and performance analysis of a computing device are described. In one embodiment, for example, an apparatus may include at least one memory and logic coupled to the at least one memory, wherein the logic is further to access at least one trace associated with at least one trace source, access timing information associated with the at least one trace, generate a plurality of waypoints for at least one trace, each of the plurality of waypoints comprising a step of at least one trace and a time stamp, and generate at least one performance benchmark log for the at least one trace, the at least one benchmark log comprising a plurality of benchmark waypoints corresponding to the plurality of waypoints.Type: GrantFiled: December 28, 2017Date of Patent: August 4, 2020Assignee: INTEL CORPORATIONInventors: Sankaran Menon, Krishna Kumar Ganesan, Rolf Kuehnis, Eija Maarit Hillevi Manninen
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Publication number: 20190042391Abstract: Techniques and apparatus for error and performance analysis of a computing device are described. In one embodiment, for example, an apparatus may include at least one memory and logic coupled to the at least one memory, wherein the logic is further to access at least one trace associated with at least one trace source, access timing information associated with the at least one trace, generate a plurality of waypoints for at least one trace, each of the plurality of waypoints comprising a step of at least one trace and a time stamp, and generate at least one performance benchmark log for the at least one trace, the at least one benchmark log comprising a plurality of benchmark waypoints corresponding to the plurality of waypoints.Type: ApplicationFiled: December 28, 2017Publication date: February 7, 2019Applicant: INTEL CORPORATIONInventors: Sankaran Menon, Krishna Kumar Ganesan, Rolf Kuehnis, Eija Maarit Hillevi Manninen
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Patent number: 9753836Abstract: In an embodiment, a debug architecture for a processor/System on Chip (SoC) etc., includes a central debug unit to receive one or more functional debug signals, the central debug unit further configured to receive debug information from at least one firmware source, at least one software source, and at least one hardware source, and to output compressed debug information; a system trace module to receive the compressed debug information and to time stamp the compressed debug information; a parallel trace interface to receive the time stamped compressed debug information and to parallelize the time stamped compressed debug information; and an output unit to output the parallelized time stamped compressed debug information on one of a plurality of output paths. Other embodiments are described and claimed.Type: GrantFiled: September 12, 2014Date of Patent: September 5, 2017Assignee: Intel CorporationInventors: Sankaran Menon, Babu Trp, Rolf Kuehnis
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Patent number: 9372768Abstract: Techniques of debugging a computing system are described herein. The techniques may include generating debug data at agents in the computing system. The techniques may include recording the debug data at a storage element, wherein the storage element is disposed in a non-core portion of the circuit interconnect accessible to the agents.Type: GrantFiled: December 26, 2013Date of Patent: June 21, 2016Assignee: Intel CorporationInventors: Jeremy Conner, Sabar Souag, Karunakara Kotary, Victor Ruybalid, Noel Eck, Ramana Rachakonda, Sankaran Menon, Lance Hacking
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Publication number: 20160077905Abstract: In an embodiment, a debug architecture for a processor/System on Chip (SoC) etc., includes a central debug unit to receive one or more functional debug signals, the central debug unit further configured to receive debug information from at least one firmware source, at least one software source, and at least one hardware source, and to output compressed debug information; a system trace module to receive the compressed debug information and to time stamp the compressed debug information; a parallel trace interface to receive the time stamped compressed debug information and to parallelize the time stamped compressed debug information; and an output unit to output the parallelized time stamped compressed debug information on one of a plurality of output paths. Other embodiments are described and claimed.Type: ApplicationFiled: September 12, 2014Publication date: March 17, 2016Inventors: Sankaran Menon, Babu Trp, Rolf Kuehnis
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Publication number: 20160018462Abstract: Described is an apparatus which comprises: a first voltage regulator (VR) having a reference input node; and a first multiplexer to provide a reference voltage to the reference input node and operable to select one of at least two different reference voltages as the reference voltage.Type: ApplicationFiled: July 18, 2014Publication date: January 21, 2016Inventors: SANKARAN MENON, VASUDEV BIBIKAR, SAHAJANANDA REDDY P, SUNGHYUN KOH, NAVEENDRAN BALASINGAM
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Publication number: 20150186232Abstract: Techniques of debugging a computing system are described herein. The techniques may include generating debug data at agents in the computing system. The techniques may include recording the debug data at a storage element, wherein the storage element is disposed in a non-core portion of the circuit interconnect accessible to the agents.Type: ApplicationFiled: December 26, 2013Publication date: July 2, 2015Inventors: Jeremy Conner, Sabar Souag, Karunakara Kotary, Victor Ruybalid, Noel Eck, Ramana Rachakonda, Sankaran Menon, Lance Hacking
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Patent number: 8312309Abstract: A technique to promote determinism among multiple clocking domains within a computer system or integrated circuit, In one embodiment, one or more execution units are placed in a deterministic state with respect to multiple clocks within a processor system having a number of different clocking domains.Type: GrantFiled: March 5, 2008Date of Patent: November 13, 2012Assignee: Intel CorporationInventors: Eric L. Hendrickson, Sanjoy Mondal, Larry Thatcher, William Hodges, Lance Hacking, Sankaran Menon
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Publication number: 20090228736Abstract: A technique to promote determinism among multiple clocking domains within a computer system or integrated circuit, In one embodiment, one or more execution units are placed in a deterministic state with respect to multiple clocks within a processor system having a number of different clocking domains.Type: ApplicationFiled: March 5, 2008Publication date: September 10, 2009Inventors: Eric L. Hendrickson, Sanjoy Mondal, Larry Thatcher, William Hodges, Lance Hacking, Sankaran Menon
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Publication number: 20080104466Abstract: The inputs to an embedded core, e.g., the core terminals, may not be directly connected to pins on the SoC. The lack of direct access to an embedded core's terminals may complicate testing of the embedded core. A test wrapper including boundary scan test (BST) cells may be used to test an embedded core. Dual function BST/ATPG (Automatic Test Pattern Generation) cells may be used to perform both BST and ATPG tests on embedded cores. A BIST (Built-In Self Test) controller supporting a “resume” mode in addition to a “pass/fail” mode may be used to compensate for timing latencies introduced by pipeline staging in an embedded memory array.Type: ApplicationFiled: December 21, 2007Publication date: May 1, 2008Inventors: Sankaran Menon, Luis Basto, Tien Dinh, Thomas Tomazin, Juan Revilla
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Publication number: 20070136564Abstract: Apparatus including a save path to connect an output of a first latch of a first save/restore cell of a save/restore chain to an input of a second latch of the first save/restore cell, a restore path to connect an output from the second latch to an input of the first latch, and a scan path to connect the output of the second latch to an input of a second save/restore cell of the save/restore chain. The apparatus is useful for fast context switching.Type: ApplicationFiled: December 14, 2005Publication date: June 14, 2007Inventors: Sankaran Menon, John Fernando, Ravi Kolagotla
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Publication number: 20060075296Abstract: In some embodiments, a method, apparatus and system for data integrity of state retentive elements under low power modes are generally presented. In this regard, an integrity agent is introduced to generate one or more error checking bits for content within a logic block in response to an indication associated with a request to enter a low power mode. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: September 30, 2004Publication date: April 6, 2006Inventors: Sankaran Menon, Thomas Mozdzen