Abstract: Aspects of the present disclosure provide a method of operating a system-on-chip (SoC). The method includes determining efficiency of a memory of the SoC over a defined period of time, calculating an adjusted bandwidth for operating the memory based on the determined efficiency, and adjusting at least one of a voltage or a clock of the memory corresponding to the adjusted bandwidth.

Abstract: Certain aspects of the present disclosure provide techniques for increasing processor caching efficiency by cache data pattern optimization. One embodiment includes a method for managing data in a cache, including: receiving data to be cached at the cache; determining that the data to be cached matches a predefined data pattern; and updating a tag RAM associated with the cache with a pattern tag comprising tag bits and pattern bits, wherein the pattern bits match the predefined data pattern.

Abstract: Aspects of the present disclosure provide a method of operating a system-on-chip (SoC). The method includes determining efficiency of a memory of the SoC over a defined period of time, calculating an adjusted bandwidth for operating the memory based on the determined efficiency, and adjusting at least one of a voltage or a clock of the memory corresponding to the adjusted bandwidth.

Abstract: Dynamic predictive wake-up techniques are disclosed. A central processing unit (CPU) may initiate an input/output (I/O) transfer. The CPU may ascertain if a predicted time for the transfer exceeds an amount of time required to enter and exit a low-power mode and enter the low-power mode after the transfer is initiated. An I/O controller may calculate how long the transfer will take and compare that calculation to a known exit latency associated with the CPU. The calculated value is decremented by the amount of the known exit latency and the I/O controller may generate an early wake command at the decremented value. The CPU receives the early wake command and wakes such that the CPU is awake and ready to process data at conclusion of the transfer.

Abstract: A portable computing device is arranged with one or more subsystems that include a processor and a memory management unit arranged to execute threads under a subsystem level operating system. The processor is in communication with a primary memory. A first area of the primary memory is used for storing time critical code and data. A second area is available for demand pages required by a thread executing in the processor. A secondary memory is accessible to a hypervisor. The processor generates an interrupt when a page fault is detected. The hypervisor, in response to the interrupt, initiates a direct memory transfer of information in the secondary memory to the second area available for demand pages in the primary memory. Upon completion of the transfer, the hypervisor communicates a task complete acknowledgement to the processor.