Abstract: This invention identifies vehicles on arrival, and matches exiting vehicles to their corresponding entry event. The matching process uses primarily optical inputs. The system uses at least one camera to capture not only the vehicle license plate but also the visual features. A “signature” formed out of the optical features of the vehicle is compared against the pre-generated signatures of vehicles in a whitelist, and the best match is identified. The “signature” for each exiting vehicle is compared against all signatures of vehicles that entered the garage. A plurality of filters reduce the possible matching candidates based on factors like license plate based edit distance, location information of vehicle owner. Synchronizing a database in each local processing unit (LPU) with a central database enables signature from images from sites that have good license plate reads, to assist in authentication in other sites where the reads are lower quality.

Abstract: An edge device for image processing includes a series of linked components which can be independently optimized. A specialized change detector which optimizes the events collected at the expense of false positives is accompanied by a trainable module, which uses training feedback to reduce the false positives over time. A “look ahead module” peeks ahead in time and determines whether an inference pipeline needs to run. This allocates a definite amount of time for the validation and training module. The training module is operated in terms of a quantum of time. Processing time during phases of no scene activity is reserved to carry out training. A lightweight detector and the classifier are trainable modules. A site optimizer is made up of rules and sub-modules using spatio-temporal heuristics to handle specific false positives while optimally combining the change detector and inference module results.

Abstract: A system and method for identification and authentication of vehicles using imaging to develop a vehicle signature based off of both license plate recognition and identification of distinct features of the vehicle. The system may cross-reference the vehicle signature against databases of known vehicle signatures to authenticate the vehicle and to determine whether or not the vehicle is on a whitelist.

Abstract: A method for generating a high-dynamic-range (HDR) image using an imaging device is provided. The method includes capturing a long-exposure (LE) image, a short-exposure (SE) image, and an auto-exposure (AE) image of a scene, estimating motion information in the SE image and the LE image based on a reference image which is determined based on an image statistics parameter, aligning the SE image and the LE image using the motion information, generating a pixel-weight coefficient for each of the SE image, the LE image, and the AE image, generating an overlapped region mask corresponding to an overlapped region in each of the SE image, the LE image and the LE image, determining a modified pixel-weight coefficient in the overlapped region mask and correcting a brightness difference, and generating an HDR image from the SE image, the LE image and the AE image using the modified at least one pixel-weight coefficient.

Abstract: A method of selecting capture configuration based on scene analysis and an image capturing device are provided. The method includes analyzing by a processor, a scene currently being captured by an image capturing device having a plurality of imaging sensors, identifying a current image capturing mode of the image capturing device, setting at least one capture parameter for the plurality of the imaging sensors, upon determining that the at least one capture parameter of the current image capturing mode has to be changed, and determining a timing sequence for triggering the plurality of imaging sensors to capture a plurality of image frames based on the set at least one capture parameter.

Abstract: A method for generating a high-dynamic-range (HDR) image using an imaging device is provided. The method includes capturing a long-exposure (LE) image, a short-exposure (SE) image, and an auto-exposure (AE) image of a scene, estimating motion information in the SE image and the LE image based on a reference image which is determined based on an image statistics parameter, aligning the SE image and the LE image using the motion information, generating a pixel-weight coefficient for each of the SE image, the LE image, and the AE image, generating an overlapped region mask corresponding to an overlapped region in each of the SE image, the LE image and the LE image, determining a modified pixel-weight coefficient in the overlapped region mask and correcting a brightness difference, and generating an HDR image from the SE image, the LE image and the AE image using the modified at least one pixel-weight coefficient.

Abstract: A method of selecting capture configuration based on scene analysis and an image capturing device are provided. The method includes analyzing by a processor, a scene currently being captured by an image capturing device having a plurality of imaging sensors, identifying a current image capturing mode of the image capturing device, setting at least one capture parameter for the plurality of the imaging sensors, upon determining that the at least one capture parameter of the current image capturing mode has to be changed, and determining a timing sequence for triggering the plurality of imaging sensors to capture a plurality of image frames based on the set at least one capture parameter.

Abstract: A motion estimation algorithm finds the best match for a given block or macroblock so that the resulting error signal has very low energy level which is computed, for e.g., by the SAD method. The motion estimation algorithm also provides for an optional sub-pixel level estimation and an inter4v search, and allows for restricting the number of searches for a Frame-frame ME (motion estimation) using Top-Top and Bottom-Bottom field MEs. The algorithm provides for a selective early exit and enables selecting a suitable search area with N candidate points (4 to 8) for starting the search. The search is conducted progressively till a minimum error signal (low energy level signal) is reached. The candidate points for search may be in a diamond shaped configuration, and there may be a plurality of successive diamond configurations, the number of which is configurable. The invention has application in MPEG-4 and H.264 standards.

Abstract: A method for achieving bit rate controlled encoding, e.g., constant bit rate, uses a bit rate control model based on bits allocated per macroblock and based on error in estimating bits consumed in an encoding process in a macroblock. The method computes bits consumed per macroblock as a function of the formed bit rate control model, and allocates bits for the macroblock. To this end, a quadratic (second order) equation is used for the model, which equation might default into a first order equation requiring fewer computations, in the event that no second order solutions exist. In one form, the bit rate control model computes the bit rate to satisfy video buffer verifier (VBV) compliance in accordance with MPEG requirements. The bit rate control model makes allowances for the type of macroblock, i.e., inter, intra or bidirectional, and provides for any frame-skips.

Abstract: A method for designing a multi-threaded processing operation that includes, e.g., multimedia encoding/decoding, uses an architecture having multiple processors and optional hardware accelerators. The method includes the steps of: identifying a desired chronological sequence of processing stages for processing input data including identifying interdependencies of said processing stages; allotting each said processing sage to a processor; staggering the processing to accommodate the interdependencies; selecting a processing operation based on said allotting to arrive at a subset of possible pipelines that offer low average processing time; and, choosing one design pipeline from said subset to result in overall timing reduction to complete said processing operation. The invention provides a multi-threaded processing pipeline that is applicable in a System-on-Chip (SoC) using a DSP and shared resources such as DMA controller and on-chip memory, for increasing the throughput.

Abstract: A motion estimation algorithm finds the best match for a given block or macroblock so that the resulting error signal has very low energy level which is computed, for e.g., by the SAD method. The motion estimation algorithm also provides for an optional sub-pixel level estimation and an inter4v search, and allows for restricting the number of searches for a Frame-frame ME (motion estimation) using Top-Top and Bottom-Bottom field MEs. The algorithm provides for a selective early exit and enables selecting a suitable search area with N candidate points (4 to 8) for starting the search. The search is conducted progressively till a minimum error signal (low energy level signal) is reached. The candidate points for search may be in a diamond shaped configuration, and there may be a plurality of successive diamond configurations, the number of which is configurable. The invention has application in MPEG-4 and H.264 standards.

Abstract: A method for designing a multi-threaded processing operation that includes, e.g., multimedia encoding/decoding, uses an architecture having multiple processors and optional hardware accelerators. The method includes the steps of: identifying a desired chronological sequence of processing stages for processing input data including identifying interdependencies of said processing stages; allotting each said processing sage to a processor; staggering the processing to accommodate the interdependencies; selecting a processing operation based on said allotting to arrive at a subset of possible pipelines that offer low average processing time; and, choosing one design pipeline from said subset to result in overall timing reduction to complete said processing operation. The invention provides a multi-threaded processing pipeline that is applicable in a System-on-Chip (SoC) using a DSP and shared resources such as DMA controller and on-chip memory, for increasing the throughput.

Abstract: A design method for implementing a high-memory algorithm for motion estimation and compensation uses a low internal memory processor and a DMA engine that interacts with the processor and the algorithm. The DMA takes care of large data transfers from an external memory to the processor internal memory and vice-versa, without using the CPU clock cycles. The design method is scalable and is suited to handle huge bandwidths without slowing down the processor. To prevent the processor from being idle during DMA, the processing is pipelined and staggered so that motion compensation is performed on an earlier block or data that is available, while DMA fetches the reference data for the current block. Several DMAs may be set up under an ISR if necessary. The invention has application in video decoders including those conforming to H.264, VC-1, and MPEG-4 ASP.

Abstract: A method for achieving bit rate controlled encoding, e.g., constant bit rate, uses a bit rate control model based on bits allocated per macroblock and based on error in estimating bits consumed in an encoding process in a macroblock. The method computes bits consumed per macroblock as a function of the formed bit rate control model, and allocates bits for the macroblock. To this end, a quadratic (second order) equation is used for the model, which equation might default into a first order equation requiring fewer computations, in the event that no second order solutions exist. In one form, the bit rate control model computes the bit rate to satisfy video buffer verifier (VBV) compliance in accordance with MPEG requirements. The bit rate control model makes allowances for the type of macroblock, i.e., inter, intra or bidirectional, and provides for any frame-skips.