Patents by Inventor Sanmati S. Kamath

Sanmati S. Kamath has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9898805
    Abstract: A method is disclosed for efficiently calculating a median value of a high-order array in a Single Instruction Multiple Data (SIMD) processor. Values of the high-order array are sorted vertically in each column followed by sorts on each individual row. After the sort, selective diagonal values of the sorted high-order array are used to form a low-order array to calculate the median of the high-order array. The median calculation using selective diagonal values of the high-order array in a low-order array significantly improves SIMD processor efficiency and throughput.
    Type: Grant
    Filed: February 10, 2016
    Date of Patent: February 20, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sanmati S. Kamath, Dipan Kumar Mandal, Wonki Choi
  • Patent number: 9665542
    Abstract: A method for determining a median value of an array of pixels in a vision system may be performed in an efficient manner using the parallel computing capabilities of a SIMD processing engine. Each column of an array may be sorted in ascending (descending) order to form a first sorted array. Each row of the first sorted array may be sorted in ascending (descending) order to form a second sorted array. A pixel may be selected as the median value from a diagonal portion of the second sorted array, wherein the diagonal portion bisects a lower value region and a higher value region of the second sorted array.
    Type: Grant
    Filed: August 8, 2014
    Date of Patent: May 30, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sanmati S. Kamath, Anoop K. Pathayapurakkal
  • Publication number: 20160232641
    Abstract: A method is disclosed for efficiently calculating a median value of a high-order array in a Single Instruction Multiple Data (SIMD) processor. Values of the high-order array are sorted vertically in each column followed by sorts on each individual row. After the sort, selective diagonal values of the sorted high-order array are used to form a low-order array to calculate the median of the high-order array. The median calculation using selective diagonal values of the high-order array in a low-order array significantly improves SIMD processor efficiency and throughput.
    Type: Application
    Filed: February 10, 2016
    Publication date: August 11, 2016
    Inventors: Sanmati S. Kamath, Dipan Kumar Mandal, Wonki Choi
  • Publication number: 20150067008
    Abstract: A method for determining a median value of an array of pixels in a vision system may be performed in an efficient manner using the parallel computing capabilities of a SIMD processing engine. Each column of an array may be sorted in ascending (descending) order to form a first sorted array. Each row of the first sorted array may be sorted in ascending (descending) order to form a second sorted array. A pixel may be selected as the median value from a diagonal portion of the second sorted array, wherein the diagonal portion bisects a lower value region and a higher value region of the second sorted array.
    Type: Application
    Filed: August 8, 2014
    Publication date: March 5, 2015
    Inventors: Sanmati S. Kamath, Anoop K. Pathayapurakkal
  • Publication number: 20110280314
    Abstract: A video decoder includes a memory (140) operable to hold entropy coded video data accessible as a bit stream, a processor (100) operable to issue at least one command for loose-coupled support and to issue at least one instruction for tightly-coupled support, a bit stream unit (110.1) coupled to said memory (140) and to said processor (100) and responsive to at least one command to provide the loose-coupled support and command-related accelerated processing of the bit stream, and a second bit stream unit (110.2) coupled to said memory (140) and to said processor (100) and responsive to said at least one instruction to provide the tightly-coupled support and instruction-related accelerated processing of the bit stream. Other encoding and decoding processors, circuits, devices, systems and processes are also disclosed.
    Type: Application
    Filed: June 15, 2010
    Publication date: November 17, 2011
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jagadeesh Sankaran, Sajish Sajayan, Sanmati S. Kamath