Abstract: In the present invention, a precharge circuit includes a precharge supply for setting equal potentials at pairs of spaced signal lines extending in parallel with respect to each other, a pair of switching elements for connecting and disconnecting respective signal lines to the supply, and a short circuit switching element for connecting and disconnecting short circuiting of the signal lines. The short circuit switching element consists of a transistor comprising a source and drain constituted by a pair of impurity regions formed underneath the pair of signal lines so as to correspond to the pair of signal lines and a gate. The gate of the transistor is formed in such a manner that gate length coincides with the widthwise direction of the pair of signal lines.

Abstract: A differential amplifier compares a potential difference between a first input (A.sub.in) and a second input (V.sub.r) and provides complementary output signals (A, A). The differential amplifier comprises a flip-flop (20) having nodes (N1, N2) and nodes (N3, N4) and a fixing means composed of N-channel FETs (33, 34) having drains connected to the nodes (N3, N4) of the flip-flop circuit (20) and sources connected to a second potential (V.sub.SS) and inverters (31, 32) having inputs to which output signals (A, A) are applied and outputs connected to gates of the N-channel FETs (33, 34). The fixing means detects a potential drop of the output signals (A, A) and fixing the nodes (N3, N4) connected to the nodes (N1, N2) to the second potential (V.sub.SS).

Abstract: A CMOS memory device has a memory cell array, formed on a substrate of a first conductive type, for storing data. The data are input and output via bit line pairs connected to the memory cell array. Sense amplifiers of the first conductive type, which are embedded in wells of a second conductive type, amplify potential differences on the bit line pairs. The sense amplifiers are connected to and driven by a sense amplifier drive signal line. The sense amplifier drive signal line also biases the wells containing the sense amplifiers, thereby preventing latch-up.

Abstract: A CMOS memory device has a memory cell array, formed on a substrate of a first conductive type, for storing data. The data are input and output via bit line pairs connected to the memory cell array. Sense amplifiers of the first conductive type, which are embedded in wells of a second conductive type, amplify potential differences on the bit line pairs. The sense amplifiers are connected to and driven by a sense amplifier drive signal line. The sense amplifier drive signal line also biases the wells containing the sense amplifiers, thereby preventing latch-up.

Abstract: A memory circuit has a Vcc post that is connected to a Vcc pad and is optionally connectable to a mode pad. The memory circuit also has N data output buffers, M of which operate regardless of whether the Vcc post is connected to the mode pad or not. These M data output buffers are all powered from the Vcc pad. The remaining N-M data output buffers operate only when the Vcc post is connected to the mode pad; at least one of these N-M data output buffers is powered from the mode pad, thereby reducing the potential drop at the Vcc pad.